From: Biju Das <biju.das.jz@bp.renesas.com>
On RSCI IP, a deadlock occurs during a FIFO overrun error, as it uses a
different register to clear the FIFO overrun error status.
Cc: stable@kernel.org
Fixes: 0666e3fe95ab ("serial: sh-sci: Add support for RZ/T2H SCI")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
* Dropped overrun_clr from struct sci_port_params_bits
* All of the CFCLR_*C clearing bits match the corresponding
CSR_*status bits. So, reused the overrun mask for irq clearing.
v1->v2:
* Split the fixes patches from original series.
---
drivers/tty/serial/sh-sci.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index b28711eeab71..53edbf1d8963 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -1198,8 +1198,16 @@ static int sci_handle_fifo_overrun(struct uart_port *port)
status = s->ops->read_reg(port, s->params->overrun_reg);
if (status & s->params->overrun_mask) {
- status &= ~s->params->overrun_mask;
- s->ops->write_reg(port, s->params->overrun_reg, status);
+ if (s->type == SCI_PORT_RSCI) {
+ /*
+ * All of the CFCLR_*C clearing bits match the corresponding
+ * CSR_*status bits. So, reuse the overrun mask for clearing.
+ */
+ s->ops->clear_SCxSR(port, s->params->overrun_mask);
+ } else {
+ status &= ~s->params->overrun_mask;
+ s->ops->write_reg(port, s->params->overrun_reg, status);
+ }
port->icount.overrun++;
--
2.43.0