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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4778bae816bsm40685815e9.0.2025.11.14.02.13.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Nov 2025 02:13:54 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby Cc: Biju Das , Geert Uytterhoeven , Wolfram Sang , Lad Prabhakar , Claudiu Beznea , Nam Cao , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, Biju Das , linux-renesas-soc@vger.kernel.org, stable@kernel.org Subject: [PATCH v3 2/2] serial: sh-sci: Fix deadlock during RSCI FIFO overrun error Date: Fri, 14 Nov 2025 10:13:47 +0000 Message-ID: <20251114101350.106699-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251114101350.106699-1-biju.das.jz@bp.renesas.com> References: <20251114101350.106699-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das On RSCI IP, a deadlock occurs during a FIFO overrun error, as it uses a different register to clear the FIFO overrun error status. Cc: stable@kernel.org Fixes: 0666e3fe95ab ("serial: sh-sci: Add support for RZ/T2H SCI") Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v2->v3: * Dropped overrun_clr from struct sci_port_params_bits * All of the CFCLR_*C clearing bits match the corresponding CSR_*status bits. So, reused the overrun mask for irq clearing. v1->v2: * Split the fixes patches from original series. --- drivers/tty/serial/sh-sci.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index b28711eeab71..53edbf1d8963 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -1198,8 +1198,16 @@ static int sci_handle_fifo_overrun(struct uart_port = *port) =20 status =3D s->ops->read_reg(port, s->params->overrun_reg); if (status & s->params->overrun_mask) { - status &=3D ~s->params->overrun_mask; - s->ops->write_reg(port, s->params->overrun_reg, status); + if (s->type =3D=3D SCI_PORT_RSCI) { + /* + * All of the CFCLR_*C clearing bits match the corresponding + * CSR_*status bits. So, reuse the overrun mask for clearing. + */ + s->ops->clear_SCxSR(port, s->params->overrun_mask); + } else { + status &=3D ~s->params->overrun_mask; + s->ops->write_reg(port, s->params->overrun_reg, status); + } =20 port->icount.overrun++; =20 --=20 2.43.0