On Fri, Oct 24, 2025 at 02:15:45PM -0500, Alex Elder wrote:
> The SpacemiT K1 SoC QSPI implementation needs to avoid shutting off the
> clock when changing its rate. Add a new quirk to indicate that disabling
> and enabling the clock should be skipped when changing its rate.
>
> Signed-off-by: Alex Elder <elder@riscstar.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> v3: - needs_clk_disable() is no longer inline
>
> drivers/spi/spi-fsl-qspi.c | 21 +++++++++++++++++----
> 1 file changed, 17 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
> index 1944e63169d36..2c030dd6facc7 100644
> --- a/drivers/spi/spi-fsl-qspi.c
> +++ b/drivers/spi/spi-fsl-qspi.c
> @@ -197,6 +197,11 @@
> */
> #define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5)
>
> +/*
> + * Do not disable the "qspi" clock when changing its rate.
> + */
> +#define QUADSPI_QUIRK_SKIP_CLK_DISABLE BIT(6)
> +
> struct fsl_qspi_devtype_data {
> unsigned int rxfifo;
> unsigned int txfifo;
> @@ -306,6 +311,11 @@ static bool needs_tdh_setting(struct fsl_qspi *q)
> return !!(q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING);
> }
>
> +static bool needs_clk_disable(struct fsl_qspi *q)
> +{
> + return !(q->devtype_data->quirks & QUADSPI_QUIRK_SKIP_CLK_DISABLE);
> +}
> +
> /*
> * An IC bug makes it necessary to rearrange the 32-bit data.
> * Later chips, such as IMX6SLX, have fixed this bug.
> @@ -536,15 +546,18 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi,
> if (needs_4x_clock(q))
> rate *= 4;
>
> - fsl_qspi_clk_disable_unprep(q);
> + if (needs_clk_disable(q))
> + fsl_qspi_clk_disable_unprep(q);
>
> ret = clk_set_rate(q->clk, rate);
> if (ret)
> return;
>
> - ret = fsl_qspi_clk_prep_enable(q);
> - if (ret)
> - return;
> + if (needs_clk_disable(q)) {
> + ret = fsl_qspi_clk_prep_enable(q);
> + if (ret)
> + return;
> + }
>
> q->selected = spi_get_chipselect(spi, 0);
>
> --
> 2.48.1
>