In the NVIDIA vGPU RFC [1], the PCI configuration space access is
required in nova-core for preparing gspVFInfo when vGPU support is
enabled. This series is the following up of the discussion with Danilo
for how to introduce support of PCI configuration space access in Rust
PCI abstrations. Bascially, we are thinking of introducing another
backend for PCI configuration space access similar with Kernel::Io.

This ideas of this series are:

- Factor out a common trait 'Io' for other accessors to share the
  same compiling/runtime check like before.

- Factor the MMIO read/write macros from the define_read! and
  define_write! macros. Thus, define_{read, write}! can be used in other
  backend.

- Add a helper to query configuration space size. This is mostly for
  runtime check.

- Implement the PCI configuration space access backend in PCI
  abstractions.

v2:

- Factor out common trait as 'Io' and keep the rest routines in original
  'Io' as 'Mmio'. (Danilo)

- Rename 'IoRaw' to 'MmioRaw'. Update the bus MMIO implemention to use
  'MmioRaw'.

- Intorduce pci::Device<Bound>::config_space(). (Danilo)

- Implement both infallible and fallible read/write routines, the device
  driver devicdes which version should be used.

Moving forward:

- Define and use register! macros.
- Introduce { cap, ecap } search and read.

RFC v1:
https://lore.kernel.org/all/20251010080330.183559-1-zhiw@nvidia.com/

[1] https://lore.kernel.org/all/20250903221111.3866249-1-zhiw@nvidia.com/

Zhi Wang (5):
  rust/io: factor common I/O helpers into Io trait and specialize
    Mmio<SIZE>
  rust: io: factor out MMIO read/write macros
  rust: pci: add a helper to query configuration space size
  rust: pci: add config space read/write support
  nova-core: test configuration routine.

 drivers/gpu/nova-core/driver.rs      |   4 +
 drivers/gpu/nova-core/regs/macros.rs |  36 +++---
 rust/kernel/io.rs                    | 161 +++++++++++++++++----------
 rust/kernel/io/mem.rs                |  16 +--
 rust/kernel/pci.rs                   |  79 ++++++++++++-
 5 files changed, 206 insertions(+), 90 deletions(-)

-- 
2.47.3

On Fri Oct 17, 2025 at 6:02 AM JST, Zhi Wang wrote:
> In the NVIDIA vGPU RFC [1], the PCI configuration space access is
> required in nova-core for preparing gspVFInfo when vGPU support is
> enabled. This series is the following up of the discussion with Danilo
> for how to introduce support of PCI configuration space access in Rust
> PCI abstrations. Bascially, we are thinking of introducing another
> backend for PCI configuration space access similar with Kernel::Io.
>
> This ideas of this series are:
>
> - Factor out a common trait 'Io' for other accessors to share the
>   same compiling/runtime check like before.
>
> - Factor the MMIO read/write macros from the define_read! and
>   define_write! macros. Thus, define_{read, write}! can be used in other
>   backend.
>
> - Add a helper to query configuration space size. This is mostly for
>   runtime check.
>
> - Implement the PCI configuration space access backend in PCI
>   abstractions.
>
> v2:
>
> - Factor out common trait as 'Io' and keep the rest routines in original
>   'Io' as 'Mmio'. (Danilo)
>
> - Rename 'IoRaw' to 'MmioRaw'. Update the bus MMIO implemention to use
>   'MmioRaw'.
>
> - Intorduce pci::Device<Bound>::config_space(). (Danilo)
>
> - Implement both infallible and fallible read/write routines, the device
>   driver devicdes which version should be used.
>
> Moving forward:
>
> - Define and use register! macros.
> - Introduce { cap, ecap } search and read.
>
> RFC v1:
> https://lore.kernel.org/all/20251010080330.183559-1-zhiw@nvidia.com/

One small nit: the title of this series 

    [PATCH v2 0/5] rust: pci: add config space read/write support, take 1

Is a tad confusing. How can this be take 1, if this is a v2? Also there
is no v1, the previous revision was a RFC.

Technically this should have been [PATCH 0/5] or [PATCH v1 0/5]. `b4` is
great to avoid this kind of problems, and a huge time saver generally
speaking. Can't recommend it enough.