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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2025 21:03:13.4921 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d1a03b75-4157-4bc4-797a-08de0cf76bb5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B36D.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6166 Content-Type: text/plain; charset="utf-8" The previous Io type combined both the generic I/O access helpers and MMIO implementation details in a single struct. To establish a cleaner layering between the I/O interface and its concrete backends, paving the way for supporting additional I/O mechanisms in the future, Io need to be factored. Factor the common helpers into a new Io trait, and moves the MMIO-specific logic into a dedicated Mmio type implementing that trait. Rename the IoRaw to MmioRaw and pdate the bus MMIO implementations to use MmioRaw. No functional change intended. Cc: Danilo Krummrich Signed-off-by: Zhi Wang --- drivers/gpu/nova-core/regs/macros.rs | 36 +++++------ rust/kernel/io.rs | 89 +++++++++++++++++----------- rust/kernel/io/mem.rs | 16 ++--- rust/kernel/pci.rs | 10 ++-- 4 files changed, 87 insertions(+), 64 deletions(-) diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index 8058e1696df9..c2a6547d58cd 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -609,7 +609,7 @@ impl $name { /// Read the register from its address in `io`. #[inline(always)] pub(crate) fn read(io: &T) -> Self where - T: ::core::ops::Deref>, + T: ::core::ops::Deref>, { Self(io.read32($offset)) } @@ -617,7 +617,7 @@ pub(crate) fn read(io: &T) -> Sel= f where /// Write the value contained in `self` to the register addres= s in `io`. #[inline(always)] pub(crate) fn write(self, io: &T) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref>, { io.write32(self.0, $offset) } @@ -629,7 +629,7 @@ pub(crate) fn alter( io: &T, f: F, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref>, F: ::core::ops::FnOnce(Self) -> Self, { let reg =3D f(Self::read(io)); @@ -652,7 +652,7 @@ pub(crate) fn read( #[allow(unused_variables)] base: &B, ) -> Self where - T: ::core::ops::Deref>, + T: ::core::ops::Deref>, B: crate::regs::macros::RegisterBase<$base>, { const OFFSET: usize =3D $name::OFFSET; @@ -673,7 +673,7 @@ pub(crate) fn write( #[allow(unused_variables)] base: &B, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref>, B: crate::regs::macros::RegisterBase<$base>, { const OFFSET: usize =3D $name::OFFSET; @@ -693,7 +693,7 @@ pub(crate) fn alter( base: &B, f: F, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref>, B: crate::regs::macros::RegisterBase<$base>, F: ::core::ops::FnOnce(Self) -> Self, { @@ -717,7 +717,7 @@ pub(crate) fn read( io: &T, idx: usize, ) -> Self where - T: ::core::ops::Deref>, + T: ::core::ops::Deref>, { build_assert!(idx < Self::SIZE); =20 @@ -734,7 +734,7 @@ pub(crate) fn write( io: &T, idx: usize ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref>, { build_assert!(idx < Self::SIZE); =20 @@ -751,7 +751,7 @@ pub(crate) fn alter( idx: usize, f: F, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref>, F: ::core::ops::FnOnce(Self) -> Self, { let reg =3D f(Self::read(io, idx)); @@ -767,7 +767,7 @@ pub(crate) fn try_read( io: &T, idx: usize, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref>, { if idx < Self::SIZE { Ok(Self::read(io, idx)) @@ -786,7 +786,7 @@ pub(crate) fn try_write( io: &T, idx: usize, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref>, { if idx < Self::SIZE { Ok(self.write(io, idx)) @@ -806,7 +806,7 @@ pub(crate) fn try_alter( idx: usize, f: F, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref>, F: ::core::ops::FnOnce(Self) -> Self, { if idx < Self::SIZE { @@ -838,7 +838,7 @@ pub(crate) fn read( base: &B, idx: usize, ) -> Self where - T: ::core::ops::Deref>, + T: ::core::ops::Deref>, B: crate::regs::macros::RegisterBase<$base>, { build_assert!(idx < Self::SIZE); @@ -860,7 +860,7 @@ pub(crate) fn write( base: &B, idx: usize ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref>, B: crate::regs::macros::RegisterBase<$base>, { build_assert!(idx < Self::SIZE); @@ -881,7 +881,7 @@ pub(crate) fn alter( idx: usize, f: F, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref>, B: crate::regs::macros::RegisterBase<$base>, F: ::core::ops::FnOnce(Self) -> Self, { @@ -900,7 +900,7 @@ pub(crate) fn try_read( base: &B, idx: usize, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref>, B: crate::regs::macros::RegisterBase<$base>, { if idx < Self::SIZE { @@ -922,7 +922,7 @@ pub(crate) fn try_write( base: &B, idx: usize, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref>, B: crate::regs::macros::RegisterBase<$base>, { if idx < Self::SIZE { @@ -945,7 +945,7 @@ pub(crate) fn try_alter( idx: usize, f: F, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref>, B: crate::regs::macros::RegisterBase<$base>, F: ::core::ops::FnOnce(Self) -> Self, { diff --git a/rust/kernel/io.rs b/rust/kernel/io.rs index ee182b0b5452..78413dc7ffcc 100644 --- a/rust/kernel/io.rs +++ b/rust/kernel/io.rs @@ -18,16 +18,16 @@ /// By itself, the existence of an instance of this structure does not pro= vide any guarantees that /// the represented MMIO region does exist or is properly mapped. /// -/// Instead, the bus specific MMIO implementation must convert this raw re= presentation into an `Io` -/// instance providing the actual memory accessors. Only by the conversion= into an `Io` structure -/// any guarantees are given. -pub struct IoRaw { +/// Instead, the bus specific MMIO implementation must convert this raw re= presentation into an +/// `Mmio` instance providing the actual memory accessors. Only by the con= version into an `Mmio` +/// structure any guarantees are given. +pub struct MmioRaw { addr: usize, maxsize: usize, } =20 -impl IoRaw { - /// Returns a new `IoRaw` instance on success, an error otherwise. +impl MmioRaw { + /// Returns a new `MmioRaw` instance on success, an error otherwise. pub fn new(addr: usize, maxsize: usize) -> Result { if maxsize < SIZE { return Err(EINVAL); @@ -62,11 +62,11 @@ pub fn maxsize(&self) -> usize { /// # Examples /// /// ```no_run -/// # use kernel::{bindings, ffi::c_void, io::{Io, IoRaw}}; +/// # use kernel::{bindings, ffi::c_void, io::{Mmio, MmioRaw}}; /// # use core::ops::Deref; /// /// // See also [`pci::Bar`] for a real example. -/// struct IoMem(IoRaw); +/// struct IoMem(MmioRaw); /// /// impl IoMem { /// /// # Safety @@ -81,7 +81,7 @@ pub fn maxsize(&self) -> usize { /// return Err(ENOMEM); /// } /// -/// Ok(IoMem(IoRaw::new(addr as usize, SIZE)?)) +/// Ok(IoMem(MmioRaw::new(addr as usize, SIZE)?)) /// } /// } /// @@ -93,11 +93,11 @@ pub fn maxsize(&self) -> usize { /// } /// /// impl Deref for IoMem { -/// type Target =3D Io; +/// type Target =3D Mmio; /// /// fn deref(&self) -> &Self::Target { /// // SAFETY: The memory range stored in `self` has been properly= mapped in `Self::new`. -/// unsafe { Io::from_raw(&self.0) } +/// unsafe { Mmio::from_raw(&self.0) } /// } /// } /// @@ -111,7 +111,7 @@ pub fn maxsize(&self) -> usize { /// # } /// ``` #[repr(transparent)] -pub struct Io(IoRaw); +pub struct Mmio(MmioRaw); =20 macro_rules! define_read { ($(#[$attr:meta])* $name:ident, $try_name:ident, $c_fn:ident -> $type_= name:ty) =3D> { @@ -172,32 +172,24 @@ pub fn $try_name(&self, value: $type_name, offset: us= ize) -> Result { }; } =20 -impl Io { - /// Converts an `IoRaw` into an `Io` instance, providing the accessors= to the MMIO mapping. - /// - /// # Safety - /// - /// Callers must ensure that `addr` is the start of a valid I/O mapped= memory region of size - /// `maxsize`. - pub unsafe fn from_raw(raw: &IoRaw) -> &Self { - // SAFETY: `Io` is a transparent wrapper around `IoRaw`. - unsafe { &*core::ptr::from_ref(raw).cast() } - } - +/// Represents a region of I/O space of a fixed size. +/// +/// Provides common helpers for offset validation and address +/// calculation on top of a base address and maximum size. +/// +/// Types implementing this trait (e.g. MMIO BARs or PCI config +/// regions) can share the same accessors. +pub trait Io { /// Returns the base address of this mapping. - #[inline] - pub fn addr(&self) -> usize { - self.0.addr() - } + fn addr(&self) -> usize; =20 /// Returns the maximum size of this mapping. - #[inline] - pub fn maxsize(&self) -> usize { - self.0.maxsize() - } + fn maxsize(&self) -> usize; =20 + /// Checks whether an access of type `U` at the given `offset` + /// is valid within this region. #[inline] - const fn offset_valid(offset: usize, size: usize) -> bool { + fn offset_valid(offset: usize, size: usize) -> bool { let type_size =3D core::mem::size_of::(); if let Some(end) =3D offset.checked_add(type_size) { end <=3D size && offset % type_size =3D=3D 0 @@ -206,6 +198,8 @@ const fn offset_valid(offset: usize, size: usize) ->= bool { } } =20 + /// Returns the absolute I/O address for a given `offset`. + /// Performs runtime bounds checks using [`offset_valid`] #[inline] fn io_addr(&self, offset: usize) -> Result { if !Self::offset_valid::(offset, self.maxsize()) { @@ -217,12 +211,41 @@ fn io_addr(&self, offset: usize) -> Result { self.addr().checked_add(offset).ok_or(EINVAL) } =20 + /// Returns the absolute I/O address for a given `offset`, + /// performing compile-time bound checks. #[inline] fn io_addr_assert(&self, offset: usize) -> usize { build_assert!(Self::offset_valid::(offset, SIZE)); =20 self.addr() + offset } +} + +impl Io for Mmio { + /// Returns the base address of this mapping. + #[inline] + fn addr(&self) -> usize { + self.0.addr() + } + + /// Returns the maximum size of this mapping. + #[inline] + fn maxsize(&self) -> usize { + self.0.maxsize() + } +} + +impl Mmio { + /// Converts an `MmioRaw` into an `Mmio` instance, providing the acces= sors to the MMIO mapping. + /// + /// # Safety + /// + /// Callers must ensure that `addr` is the start of a valid I/O mapped= memory region of size + /// `maxsize`. + pub unsafe fn from_raw(raw: &MmioRaw) -> &Self { + // SAFETY: `Mmio` is a transparent wrapper around `MmioRaw`. + unsafe { &*core::ptr::from_ref(raw).cast() } + } =20 define_read!(read8, try_read8, readb -> u8); define_read!(read16, try_read16, readw -> u16); diff --git a/rust/kernel/io/mem.rs b/rust/kernel/io/mem.rs index 6f99510bfc3a..93cad8539b18 100644 --- a/rust/kernel/io/mem.rs +++ b/rust/kernel/io/mem.rs @@ -11,8 +11,8 @@ use crate::io; use crate::io::resource::Region; use crate::io::resource::Resource; -use crate::io::Io; -use crate::io::IoRaw; +use crate::io::Mmio; +use crate::io::MmioRaw; use crate::prelude::*; =20 /// An IO request for a specific device and resource. @@ -195,7 +195,7 @@ pub fn new<'a>(io_request: IoRequest<'a>) -> impl PinIn= it, Error> + } =20 impl Deref for ExclusiveIoMem { - type Target =3D Io; + type Target =3D Mmio; =20 fn deref(&self) -> &Self::Target { &self.iomem @@ -209,10 +209,10 @@ fn deref(&self) -> &Self::Target { /// /// # Invariants /// -/// [`IoMem`] always holds an [`IoRaw`] instance that holds a valid pointe= r to the +/// [`IoMem`] always holds an [`MmioRaw`] instance that holds a valid poin= ter to the /// start of the I/O memory mapped region. pub struct IoMem { - io: IoRaw, + io: MmioRaw, } =20 impl IoMem { @@ -247,7 +247,7 @@ fn ioremap(resource: &Resource) -> Result { return Err(ENOMEM); } =20 - let io =3D IoRaw::new(addr as usize, size)?; + let io =3D MmioRaw::new(addr as usize, size)?; let io =3D IoMem { io }; =20 Ok(io) @@ -270,10 +270,10 @@ fn drop(&mut self) { } =20 impl Deref for IoMem { - type Target =3D Io; + type Target =3D Mmio; =20 fn deref(&self) -> &Self::Target { // SAFETY: Safe as by the invariant of `IoMem`. - unsafe { Io::from_raw(&self.io) } + unsafe { Mmio::from_raw(&self.io) } } } diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 7fcc5f6022c1..77a8eb39ad32 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -10,7 +10,7 @@ devres::Devres, driver, error::{from_result, to_result, Result}, - io::{Io, IoRaw}, + io::{Mmio, MmioRaw}, irq::{self, IrqRequest}, str::CStr, sync::aref::ARef, @@ -313,7 +313,7 @@ pub struct Device( /// memory mapped PCI bar and its size. pub struct Bar { pdev: ARef, - io: IoRaw, + io: MmioRaw, num: i32, } =20 @@ -349,7 +349,7 @@ fn new(pdev: &Device, num: u32, name: &CStr) -> Result<= Self> { return Err(ENOMEM); } =20 - let io =3D match IoRaw::new(ioptr, len as usize) { + let io =3D match MmioRaw::new(ioptr, len as usize) { Ok(io) =3D> io, Err(err) =3D> { // SAFETY: @@ -403,11 +403,11 @@ fn drop(&mut self) { } =20 impl Deref for Bar { - type Target =3D Io; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2025 21:03:33.7456 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bc0bf8f6-8961-4a24-ed91-08de0cf777ba X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9190 Content-Type: text/plain; charset="utf-8" Refactor the existing MMIO accessors to use common call macros instead of inlining the bindings calls in each `define_{read,write}!` expansion. This factoring separates the common offset/bounds checks from the low-level call pattern, making it easier to add additional I/O accessor families. No functional change intended. Signed-off-by: Zhi Wang --- rust/kernel/io.rs | 72 ++++++++++++++++++++++++++++++----------------- 1 file changed, 46 insertions(+), 26 deletions(-) diff --git a/rust/kernel/io.rs b/rust/kernel/io.rs index 78413dc7ffcc..78f7bbc945ad 100644 --- a/rust/kernel/io.rs +++ b/rust/kernel/io.rs @@ -4,6 +4,8 @@ //! //! C header: [`include/asm-generic/io.h`](srctree/include/asm-generic/io.= h) =20 +use kernel::error::Error; + use crate::error::{code::EINVAL, Result}; use crate::{bindings, build_assert, ffi::c_void}; =20 @@ -113,8 +115,23 @@ pub fn maxsize(&self) -> usize { #[repr(transparent)] pub struct Mmio(MmioRaw); =20 +macro_rules! call_mmio_read { + ($c_fn:ident, $self:ident, $offset:expr, $type:ty, $addr:expr) =3D> { + // SAFETY: By the type invariant `addr` is a valid address for MMI= O operations. + Ok::<$type, Error>(unsafe { bindings::$c_fn($addr as *const c_void= ) as $type }) + }; +} + +macro_rules! call_mmio_write { + ($c_fn:ident, $self:ident, $offset:expr, $ty:ty, $addr:expr, $value:ex= pr) =3D> { + // SAFETY: By the type invariant `addr` is a valid address for MMI= O operations. + Ok::<(), Error>(unsafe { bindings::$c_fn($value, $addr as *mut c_v= oid) }) + }; +} + macro_rules! define_read { - ($(#[$attr:meta])* $name:ident, $try_name:ident, $c_fn:ident -> $type_= name:ty) =3D> { + ($(#[$attr:meta])* $name:ident, $try_name:ident, $call_macro:ident, $c= _fn:ident -> + $type_name:ty) =3D> { /// Read IO data from a given offset known at compile time. /// /// Bound checks are performed on compile time, hence if the offse= t is not known at compile @@ -122,10 +139,9 @@ macro_rules! define_read { $(#[$attr])* #[inline] pub fn $name(&self, offset: usize) -> $type_name { - let addr =3D self.io_addr_assert::<$type_name>(offset); + let _addr =3D self.io_addr_assert::<$type_name>(offset); =20 - // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. - unsafe { bindings::$c_fn(addr as *const c_void) } + $call_macro!($c_fn, self, offset, $type_name, _addr).unwrap_or= (!0) } =20 /// Read IO data from a given offset. @@ -134,16 +150,18 @@ pub fn $name(&self, offset: usize) -> $type_name { /// out of bounds. $(#[$attr])* pub fn $try_name(&self, offset: usize) -> Result<$type_name> { - let addr =3D self.io_addr::<$type_name>(offset)?; + let _addr =3D self.io_addr::<$type_name>(offset)?; =20 // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. - Ok(unsafe { bindings::$c_fn(addr as *const c_void) }) + $call_macro!($c_fn, self, offset, $type_name, _addr) } }; } +pub(crate) use define_read; =20 macro_rules! define_write { - ($(#[$attr:meta])* $name:ident, $try_name:ident, $c_fn:ident <- $type_= name:ty) =3D> { + ($(#[$attr:meta])* $name:ident, $try_name:ident, $call_macro:ident, $c= _fn:ident <- + $type_name:ty) =3D> { /// Write IO data from a given offset known at compile time. /// /// Bound checks are performed on compile time, hence if the offse= t is not known at compile @@ -151,10 +169,9 @@ macro_rules! define_write { $(#[$attr])* #[inline] pub fn $name(&self, value: $type_name, offset: usize) { - let addr =3D self.io_addr_assert::<$type_name>(offset); + let _addr =3D self.io_addr_assert::<$type_name>(offset); =20 - // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. - unsafe { bindings::$c_fn(value, addr as *mut c_void) } + let _ =3D $call_macro!($c_fn, self, offset, $type_name, _addr,= value); } =20 /// Write IO data from a given offset. @@ -163,14 +180,13 @@ pub fn $name(&self, value: $type_name, offset: usize)= { /// out of bounds. $(#[$attr])* pub fn $try_name(&self, value: $type_name, offset: usize) -> Resul= t { - let addr =3D self.io_addr::<$type_name>(offset)?; + let _addr =3D self.io_addr::<$type_name>(offset)?; =20 - // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. - unsafe { bindings::$c_fn(value, addr as *mut c_void) } - Ok(()) + $call_macro!($c_fn, self, offset, $type_name, _addr, value) } }; } +pub(crate) use define_write; =20 /// Represents a region of I/O space of a fixed size. /// @@ -247,43 +263,47 @@ pub unsafe fn from_raw(raw: &MmioRaw) -> &Self { unsafe { &*core::ptr::from_ref(raw).cast() } } =20 - define_read!(read8, try_read8, readb -> u8); - define_read!(read16, try_read16, readw -> u16); - define_read!(read32, try_read32, readl -> u32); + define_read!(read8, try_read8, call_mmio_read, readb -> u8); + define_read!(read16, try_read16, call_mmio_read, readw -> u16); + define_read!(read32, try_read32, call_mmio_read, readl -> u32); define_read!( #[cfg(CONFIG_64BIT)] read64, try_read64, + call_mmio_read, readq -> u64 ); =20 - define_read!(read8_relaxed, try_read8_relaxed, readb_relaxed -> u8); - define_read!(read16_relaxed, try_read16_relaxed, readw_relaxed -> u16); - define_read!(read32_relaxed, try_read32_relaxed, readl_relaxed -> u32); + define_read!(read8_relaxed, try_read8_relaxed, call_mmio_read, readb_r= elaxed -> u8); + define_read!(read16_relaxed, try_read16_relaxed, call_mmio_read, readw= _relaxed -> u16); + define_read!(read32_relaxed, try_read32_relaxed, call_mmio_read, readl= _relaxed -> u32); define_read!( #[cfg(CONFIG_64BIT)] read64_relaxed, try_read64_relaxed, + call_mmio_read, readq_relaxed -> u64 ); =20 - define_write!(write8, try_write8, writeb <- u8); - define_write!(write16, try_write16, writew <- u16); - define_write!(write32, try_write32, writel <- u32); + define_write!(write8, try_write8, call_mmio_write, writeb <- u8); + define_write!(write16, try_write16, call_mmio_write, writew <- u16); + define_write!(write32, try_write32, call_mmio_write, writel <- u32); define_write!( #[cfg(CONFIG_64BIT)] write64, try_write64, + call_mmio_write, writeq <- u64 ); =20 - define_write!(write8_relaxed, try_write8_relaxed, writeb_relaxed <- u8= ); - define_write!(write16_relaxed, try_write16_relaxed, writew_relaxed <- = u16); - define_write!(write32_relaxed, try_write32_relaxed, writel_relaxed <- = u32); + define_write!(write8_relaxed, try_write8_relaxed, call_mmio_write, wri= teb_relaxed <- u8); + define_write!(write16_relaxed, try_write16_relaxed, call_mmio_write, w= ritew_relaxed <- u16); + define_write!(write32_relaxed, try_write32_relaxed, call_mmio_write, w= ritel_relaxed <- u32); define_write!( #[cfg(CONFIG_64BIT)] write64_relaxed, try_write64_relaxed, + call_mmio_write, writeq_relaxed <- u64 ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2025 21:03:14.3674 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c61a2901-ab5b-4b1e-c318-08de0cf76c3b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B36F.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6873 Content-Type: text/plain; charset="utf-8" Expose a safe Rust wrapper for the `cfg_size` field of `struct pci_dev`, allowing drivers to query the size of a device's configuration space. This is useful for code that needs to know whether the device supports extended configuration space (e.g. 256 vs 4096 bytes) when accessing PCI configuration registers and apply runtime checks. Signed-off-by: Zhi Wang --- rust/kernel/pci.rs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 77a8eb39ad32..34729c6f5665 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -514,6 +514,12 @@ pub fn pci_class(&self) -> Class { // SAFETY: `self.as_raw` is a valid pointer to a `struct pci_dev`. Class::from_raw(unsafe { (*self.as_raw()).class }) } + + /// Returns the size of configuration space. + pub fn cfg_size(&self) -> i32 { + // SAFETY: `self.as_raw` is a valid pointer to a `struct pci_dev`. + unsafe { (*self.as_raw()).cfg_size } + } } =20 impl Device { --=20 2.47.3 From nobody Sun Feb 8 06:55:40 2026 Received: from DM5PR21CU001.outbound.protection.outlook.com (mail-centralusazon11011052.outbound.protection.outlook.com [52.101.62.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D4422E62D4; Thu, 16 Oct 2025 21:03:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.62.52 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760648619; cv=fail; b=RX1uxebNAaID5f8t//D7hxoulaRaQfXCu6MOL/g0KCFCki/bB4HG4nwCGL42bXLFgRbJipEyWVTLstqsrS4bsXMvGB4uJ+9/pGg/qBnBUIO/qlCGhDl4l4pADSa/smhIpRugA6m90FnX6Ow0+K8n8Mih4LeF7FkrLjC550eFLd8= ARC-Message-Signature: i=2; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2025 21:03:34.8540 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9cbf7484-06a0-43a2-0ef1-08de0cf77864 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4132 Content-Type: text/plain; charset="utf-8" Introduce a `ConfigSpace` wrapper in Rust PCI abstraction to provide safe accessors for PCI configuration space. The new type implements the `Io` trait to share offset validation and bound-checking logic with others. Cc: Danilo Krummrich Signed-off-by: Zhi Wang --- rust/kernel/pci.rs | 65 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 34729c6f5665..d7e0f18169d7 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -10,7 +10,8 @@ devres::Devres, driver, error::{from_result, to_result, Result}, - io::{Mmio, MmioRaw}, + io::{define_read, define_write}, + io::{Io, Mmio, MmioRaw}, irq::{self, IrqRequest}, str::CStr, sync::aref::ARef, @@ -305,6 +306,63 @@ pub struct Device( PhantomData, ); =20 +/// Represents the PCI configuration space of a device. +/// +/// Provides typed read and write accessors for configuration registers +/// using the standard `pci_read_config_*` and `pci_write_config_*` helper= s. +/// +/// The generic const parameter `SIZE` can be used to indicate the +/// maximum size of the configuration space (e.g. 256 bytes for legacy, +/// 4096 bytes for extended config space). The actual size is obtained +/// from the underlying `struct pci_dev` via [`Device::cfg_size`]. +pub struct ConfigSpace<'a, const SIZE: usize =3D 4096> { + pdev: &'a Device, +} + +impl<'a, const SIZE: usize> Io for ConfigSpace<'a, SIZE> { + /// Returns the base address of this mapping. + #[inline] + fn addr(&self) -> usize { + 0 + } + + /// Returns the maximum size of this mapping. + #[inline] + fn maxsize(&self) -> usize { + self.pdev.cfg_size() as usize + } +} + +macro_rules! call_config_read { + ($c_fn:ident, $self:ident, $offset:expr, $ty:ty, $_addr:expr) =3D> {{ + let mut val: $ty =3D 0; + let ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $offset = as i32, &mut val) }; + (ret =3D=3D 0) + .then_some(Ok(val)) + .unwrap_or_else(|| Err(Error::from_errno(ret))) + }}; +} + +macro_rules! call_config_write { + ($c_fn:ident, $self:ident, $offset:expr, $ty:ty, $_addr:expr, $value:e= xpr) =3D> {{ + let ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $offset = as i32, $value) }; + (ret =3D=3D 0) + .then_some(Ok(())) + .unwrap_or_else(|| Err(Error::from_errno(ret))) + }}; +} + +#[allow(dead_code)] +impl<'a, const SIZE: usize> ConfigSpace<'a, SIZE> { + define_read!(read8, try_read8, call_config_read, pci_read_config_byte = -> u8); + define_read!(read16, try_read16, call_config_read, pci_read_config_wor= d -> u16); + define_read!(read32, try_read32, call_config_read, pci_read_config_dwo= rd -> u32); + + define_write!(write8, try_write8, call_config_write, pci_write_config_= byte <- u8); + define_write!(write16, try_write16, call_config_write, pci_write_confi= g_word <- u16); + define_write!(write32, try_write32, call_config_write, pci_write_confi= g_dword <- u32); +} + /// A PCI BAR to perform I/O-Operations on. /// /// # Invariants @@ -582,6 +640,11 @@ pub fn request_threaded_irq<'a, T: crate::irq::Threade= dHandler + 'static>( request, flags, name, handler, )) } + + /// Return an initialized object. + pub fn config_space<'a>(&'a self) -> Result> { + Ok(ConfigSpace { pdev: self }) + } } =20 impl Device { --=20 2.47.3 From nobody Sun Feb 8 06:55:40 2026 Received: from BYAPR05CU005.outbound.protection.outlook.com (mail-westusazon11010061.outbound.protection.outlook.com [52.101.85.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0DA32E22B5; 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