Document the device tree bindings for the DWC3 USB controller found in
Google Tensor SoCs, starting with the G5 generation.
The Tensor G5 silicon represents a complete architectural departure from
previous generations (like gs101), including entirely new clock/reset
schemes, top-level wrapper and register interface. Consequently,
existing Samsung/Exynos DWC3 USB bindings are incompatible, necessitating
this new device tree binding.
The USB controller on Tensor G5 is based on Synopsys DWC3 IP and features
Dual-Role Device single port with hibernation support.
Signed-off-by: Roy Luo <royluo@google.com>
---
.../bindings/usb/google,gs5-dwc3.yaml | 141 ++++++++++++++++++
1 file changed, 141 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml
diff --git a/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml b/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml
new file mode 100644
index 000000000000..6fadea7f41e8
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml
@@ -0,0 +1,141 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (c) 2025, Google LLC
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/google,gs5-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google Tensor Series (G5+) DWC3 USB SoC Controller
+
+maintainers:
+ - Roy Luo <royluo@google.com>
+
+description:
+ Describes the DWC3 USB controller block implemented on Google Tensor SoCs,
+ starting with the G5 generation. Based on Synopsys DWC3 IP, the controller
+ features Dual-Role Device single port with hibernation add-on.
+
+properties:
+ compatible:
+ const: google,gs5-dwc3
+
+ reg:
+ items:
+ - description: Core DWC3 IP registers.
+ - description: USB host controller configuration registers.
+ - description: USB custom interrrupts control registers.
+
+ reg-names:
+ items:
+ - const: dwc3_core
+ - const: host_cfg
+ - const: usbint_cfg
+
+ interrupts:
+ items:
+ - description: Core DWC3 interrupt.
+ - description: High speed power management event for remote wakeup from hibernation.
+ - description: Super speed power management event for remote wakeup from hibernation.
+
+ interrupt-names:
+ items:
+ - const: dwc_usb3
+ - const: hs_pme
+ - const: ss_pme
+
+ clocks:
+ items:
+ - description: Non-sticky module clock.
+ - description: Sticky module clock.
+ - description: USB2 PHY APB clock.
+
+ clock-names:
+ items:
+ - const: non_sticky
+ - const: sticky
+ - const: u2phy_apb
+
+ resets:
+ items:
+ - description: Non-sticky module reset.
+ - description: Sticky module reset.
+ - description: USB2 PHY APB reset.
+ - description: DRD bus reset.
+ - description: Top-level reset.
+
+ reset-names:
+ items:
+ - const: non_sticky
+ - const: sticky
+ - const: u2phy_apb
+ - const: drd_bus
+ - const: top
+
+ power-domains:
+ items:
+ - description: Power switchable domain, the child of top domain.
+ Turning it on puts the controller into full power state,
+ turning it off puts the controller into power gated state.
+ - description: Top domain, the parent of power switchable domain.
+ Turning it on puts the controller into power gated state,
+ turning it off completely shuts off the controller.
+
+ power-domain-names:
+ items:
+ - const: psw
+ - const: top
+
+ iommus:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - power-domains
+ - power-domain-names
+
+allOf:
+ - $ref: snps,dwc3-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ usb@c400000 {
+ compatible = "google,gs5-dwc3";
+ reg = <0 0x0c400000 0 0xd060>, <0 0x0c450000 0 0x14>, <0 0x0c450020 0 0x8>;
+ reg-names = "dwc3_core", "host_cfg", "usbint_cfg";
+ interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "dwc_usb3", "hs_pme", "ss_pme";
+ clocks = <&hsion_usbc_non_sticky_clk>, <&hsion_usbc_sticky_clk>,
+ <&hsion_u2phy_apb_clk>;
+ clock-names = "non_sticky", "sticky", "u2phy_apb";
+ resets = <&hsion_resets_usbc_non_sticky>, <&hsion_resets_usbc_sticky>,
+ <&hsion_resets_u2phy_apb>, <&hsion_resets_usb_drd_bus>,
+ <&hsion_resets_usb_top>;
+ reset-names = "non_sticky", "sticky", "u2phy_apb", "drd_bus", "top";
+ power-domains = <&hsio_n_usb_psw>, <&hsio_n_usb>;
+ power-domain-names = "psw", "top";
+ phys = <&usb_phy 0>;
+ phy-names = "usb2-phy";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,gfladj-refclk-lpm-sel-quirk;
+ snps,incr-burst-type-adjustment = <4>;
+ };
+ };
+...
--
2.51.0.740.g6adb054d12-googOn 10/10/2025 22:16, Roy Luo wrote: > Document the device tree bindings for the DWC3 USB controller found in > Google Tensor SoCs, starting with the G5 generation. > > The Tensor G5 silicon represents a complete architectural departure from > previous generations (like gs101), including entirely new clock/reset > schemes, top-level wrapper and register interface. Consequently, > existing Samsung/Exynos DWC3 USB bindings are incompatible, necessitating > this new device tree binding. > > The USB controller on Tensor G5 is based on Synopsys DWC3 IP and features > Dual-Role Device single port with hibernation support. You still mix, completely unnecessarily, subsystems. For Greg this is actually even undesired, but regardless don't do this for any cases because it just makes everything slower or more difficult to apply. Really, think how maintainers should deal with your patches. > > Signed-off-by: Roy Luo <royluo@google.com> > --- > .../bindings/usb/google,gs5-dwc3.yaml | 141 ++++++++++++++++++ > 1 file changed, 141 insertions(+) > create mode 100644 Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml > > diff --git a/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml b/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml > new file mode 100644 > index 000000000000..6fadea7f41e8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml > @@ -0,0 +1,141 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +# Copyright (c) 2025, Google LLC > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/usb/google,gs5-dwc3.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Google Tensor Series (G5+) DWC3 USB SoC Controller > + > +maintainers: > + - Roy Luo <royluo@google.com> > + > +description: > + Describes the DWC3 USB controller block implemented on Google Tensor SoCs, > + starting with the G5 generation. Based on Synopsys DWC3 IP, the controller > + features Dual-Role Device single port with hibernation add-on. > + > +properties: > + compatible: > + const: google,gs5-dwc3 > + > + reg: > + items: > + - description: Core DWC3 IP registers. > + - description: USB host controller configuration registers. > + - description: USB custom interrrupts control registers. > + > + reg-names: > + items: > + - const: dwc3_core > + - const: host_cfg > + - const: usbint_cfg > + > + interrupts: > + items: > + - description: Core DWC3 interrupt. > + - description: High speed power management event for remote wakeup from hibernation. > + - description: Super speed power management event for remote wakeup from hibernation. Wrap at 80 (see coding style) or just shorten these. > + > + interrupt-names: > + items: > + - const: dwc_usb3 So just "core"? > + - const: hs_pme > + - const: ss_pme > + > + clocks: > + items: > + - description: Non-sticky module clock. > + - description: Sticky module clock. > + - description: USB2 PHY APB clock. This looks wrong. This is not the USB2 phy, so how can it consume APB clock? > + > + clock-names: > + items: > + - const: non_sticky > + - const: sticky > + - const: u2phy_apb > + > + resets: > + items: > + - description: Non-sticky module reset. > + - description: Sticky module reset. > + - description: USB2 PHY APB reset. This as well. > + - description: DRD bus reset. > + - description: Top-level reset. > + > + reset-names: > + items: > + - const: non_sticky > + - const: sticky > + - const: u2phy_apb > + - const: drd_bus > + - const: top Best regards, Krzysztof
On Fri, Oct 10, 2025 at 5:09 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 10/10/2025 22:16, Roy Luo wrote:
> > Document the device tree bindings for the DWC3 USB controller found in
> > Google Tensor SoCs, starting with the G5 generation.
> >
> > The Tensor G5 silicon represents a complete architectural departure from
> > previous generations (like gs101), including entirely new clock/reset
> > schemes, top-level wrapper and register interface. Consequently,
> > existing Samsung/Exynos DWC3 USB bindings are incompatible, necessitating
> > this new device tree binding.
> >
> > The USB controller on Tensor G5 is based on Synopsys DWC3 IP and features
> > Dual-Role Device single port with hibernation support.
>
> You still mix, completely unnecessarily, subsystems. For Greg this is
> actually even undesired, but regardless don't do this for any cases
> because it just makes everything slower or more difficult to apply.
>
> Really, think how maintainers should deal with your patches.
>
Understood, I will separate the patches into two distinct series: one for
the controller and one for the PHY.
Appreciate the feedback and the explanation.
> >
> > Signed-off-by: Roy Luo <royluo@google.com>
> > ---
> > .../bindings/usb/google,gs5-dwc3.yaml | 141 ++++++++++++++++++
> > 1 file changed, 141 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml b/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml
> > new file mode 100644
> > index 000000000000..6fadea7f41e8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml
> > @@ -0,0 +1,141 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +# Copyright (c) 2025, Google LLC
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/usb/google,gs5-dwc3.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Google Tensor Series (G5+) DWC3 USB SoC Controller
> > +
> > +maintainers:
> > + - Roy Luo <royluo@google.com>
> > +
> > +description:
> > + Describes the DWC3 USB controller block implemented on Google Tensor SoCs,
> > + starting with the G5 generation. Based on Synopsys DWC3 IP, the controller
> > + features Dual-Role Device single port with hibernation add-on.
> > +
> > +properties:
> > + compatible:
> > + const: google,gs5-dwc3
> > +
> > + reg:
> > + items:
> > + - description: Core DWC3 IP registers.
> > + - description: USB host controller configuration registers.
> > + - description: USB custom interrrupts control registers.
> > +
> > + reg-names:
> > + items:
> > + - const: dwc3_core
> > + - const: host_cfg
> > + - const: usbint_cfg
> > +
> > + interrupts:
> > + items:
> > + - description: Core DWC3 interrupt.
> > + - description: High speed power management event for remote wakeup from hibernation.
> > + - description: Super speed power management event for remote wakeup from hibernation.
>
> Wrap at 80 (see coding style) or just shorten these.
Ack, will fix it in the next patch.
>
> > +
> > + interrupt-names:
> > + items:
> > + - const: dwc_usb3
>
> So just "core"?
I'd prefer to stick to "dwc_usb3" as that's
1. more expressive by referring to the underlying IP name,
2. consistent with established dwc3 bindings such as
Documentation/devicetree/bindings/usb/snps,dwc3.yaml,
Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml,
unless you have a strong preference for the alternative naming.
>
> > + - const: hs_pme
> > + - const: ss_pme
> > +
> > + clocks:
> > + items:
> > + - description: Non-sticky module clock.
> > + - description: Sticky module clock.
> > + - description: USB2 PHY APB clock.
>
> This looks wrong. This is not the USB2 phy, so how can it consume APB clock?
That's a fair point, I'll look into the necessity and placement of this specific
clk/reset and get back.
Thanks,
Roy Luo
>
> > +
> > + clock-names:
> > + items:
> > + - const: non_sticky
> > + - const: sticky
> > + - const: u2phy_apb
> > +
> > + resets:
> > + items:
> > + - description: Non-sticky module reset.
> > + - description: Sticky module reset.
> > + - description: USB2 PHY APB reset.
>
> This as well.
>
> > + - description: DRD bus reset.
> > + - description: Top-level reset.
> > +
> > + reset-names:
> > + items:
> > + - const: non_sticky
> > + - const: sticky
> > + - const: u2phy_apb
> > + - const: drd_bus
> > + - const: top
>
>
> Best regards,
> Krzysztof
On 14/10/2025 03:40, Roy Luo wrote: > On Fri, Oct 10, 2025 at 5:09 PM Krzysztof Kozlowski <krzk@kernel.org> wrote: >> >> On 10/10/2025 22:16, Roy Luo wrote: >>> Document the device tree bindings for the DWC3 USB controller found in >>> Google Tensor SoCs, starting with the G5 generation. >>> >>> The Tensor G5 silicon represents a complete architectural departure from >>> previous generations (like gs101), including entirely new clock/reset >>> schemes, top-level wrapper and register interface. Consequently, >>> existing Samsung/Exynos DWC3 USB bindings are incompatible, necessitating >>> this new device tree binding. >>> >>> The USB controller on Tensor G5 is based on Synopsys DWC3 IP and features >>> Dual-Role Device single port with hibernation support. >> >> You still mix, completely unnecessarily, subsystems. For Greg this is >> actually even undesired, but regardless don't do this for any cases >> because it just makes everything slower or more difficult to apply. >> >> Really, think how maintainers should deal with your patches. >> > > Understood, I will separate the patches into two distinct series: one for > the controller and one for the PHY. > Appreciate the feedback and the explanation. > >>> >>> Signed-off-by: Roy Luo <royluo@google.com> >>> --- >>> .../bindings/usb/google,gs5-dwc3.yaml | 141 ++++++++++++++++++ >>> 1 file changed, 141 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml b/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml >>> new file mode 100644 >>> index 000000000000..6fadea7f41e8 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml >>> @@ -0,0 +1,141 @@ >>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >>> +# Copyright (c) 2025, Google LLC >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/usb/google,gs5-dwc3.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Google Tensor Series (G5+) DWC3 USB SoC Controller >>> + >>> +maintainers: >>> + - Roy Luo <royluo@google.com> >>> + >>> +description: >>> + Describes the DWC3 USB controller block implemented on Google Tensor SoCs, >>> + starting with the G5 generation. Based on Synopsys DWC3 IP, the controller >>> + features Dual-Role Device single port with hibernation add-on. >>> + >>> +properties: >>> + compatible: >>> + const: google,gs5-dwc3 >>> + >>> + reg: >>> + items: >>> + - description: Core DWC3 IP registers. >>> + - description: USB host controller configuration registers. >>> + - description: USB custom interrrupts control registers. >>> + >>> + reg-names: >>> + items: >>> + - const: dwc3_core >>> + - const: host_cfg >>> + - const: usbint_cfg >>> + >>> + interrupts: >>> + items: >>> + - description: Core DWC3 interrupt. >>> + - description: High speed power management event for remote wakeup from hibernation. >>> + - description: Super speed power management event for remote wakeup from hibernation. >> >> Wrap at 80 (see coding style) or just shorten these. > > Ack, will fix it in the next patch. > >> >>> + >>> + interrupt-names: >>> + items: >>> + - const: dwc_usb3 >> >> So just "core"? > > I'd prefer to stick to "dwc_usb3" as that's > 1. more expressive by referring to the underlying IP name, But that's completely redundant name. > 2. consistent with established dwc3 bindings such as > Documentation/devicetree/bindings/usb/snps,dwc3.yaml, If you use only one interrupt. You don't use one interrupt here. > Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml, > unless you have a strong preference for the alternative naming. Such namings are discouraged, because they tell absolutely nothing. Also, schematics or datasheets usually do not use them, either. Best regards, Krzysztof
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