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AJvYcCU25wn/z0DC9V7WF6CNJvQ+4YZf6D6dnYbZgJjROPKY5/x+ETWSyLk6c0+xIUP9WwzQ0I63l+GpcEUeF3g=@vger.kernel.org X-Gm-Message-State: AOJu0Yzyr65zh8rWsx7HEyV1taAQabOyDnJq+j7L1/EOiOz2lprVRn82 RHWFaGrdmkPEAx237+hjGhyXgRvortS6OiPfvBkVeJ2L7SRQQYS6bzr7Wo+x/3LnVkY2t3++dNK NDu4uLw== X-Google-Smtp-Source: AGHT+IFk8ClGIAy+ZveXDAUA46gMVmfQcViJcyf3PjbmPLP8E3Q60Y+VuC/rLX+rN4bo089j/56MJ/qKNBU= X-Received: from pjbfr18.prod.google.com ([2002:a17:90a:e2d2:b0:33b:51fe:1a90]) (user=royluo job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:1e07:b0:339:f09b:d372 with SMTP id 98e67ed59e1d1-33b513b4c91mr19379313a91.23.1760127382638; Fri, 10 Oct 2025 13:16:22 -0700 (PDT) Date: Fri, 10 Oct 2025 20:16:04 +0000 In-Reply-To: <20251010201607.1190967-1-royluo@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251010201607.1190967-1-royluo@google.com> X-Mailer: git-send-email 2.51.0.740.g6adb054d12-goog Message-ID: <20251010201607.1190967-2-royluo@google.com> Subject: [PATCH v3 1/4] dt-bindings: usb: dwc3: Add Google Tensor G5 DWC3 From: Roy Luo To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Thinh Nguyen , Philipp Zabel , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus Cc: Joy Chakraborty , Naveen Kumar , Roy Luo , Badhri Jagan Sridharan , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the device tree bindings for the DWC3 USB controller found in Google Tensor SoCs, starting with the G5 generation. The Tensor G5 silicon represents a complete architectural departure from previous generations (like gs101), including entirely new clock/reset schemes, top-level wrapper and register interface. Consequently, existing Samsung/Exynos DWC3 USB bindings are incompatible, necessitating this new device tree binding. The USB controller on Tensor G5 is based on Synopsys DWC3 IP and features Dual-Role Device single port with hibernation support. Signed-off-by: Roy Luo --- .../bindings/usb/google,gs5-dwc3.yaml | 141 ++++++++++++++++++ 1 file changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/google,gs5-dwc3.y= aml diff --git a/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml b/D= ocumentation/devicetree/bindings/usb/google,gs5-dwc3.yaml new file mode 100644 index 000000000000..6fadea7f41e8 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) 2025, Google LLC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/google,gs5-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google Tensor Series (G5+) DWC3 USB SoC Controller + +maintainers: + - Roy Luo + +description: + Describes the DWC3 USB controller block implemented on Google Tensor SoC= s, + starting with the G5 generation. Based on Synopsys DWC3 IP, the controll= er + features Dual-Role Device single port with hibernation add-on. + +properties: + compatible: + const: google,gs5-dwc3 + + reg: + items: + - description: Core DWC3 IP registers. + - description: USB host controller configuration registers. + - description: USB custom interrrupts control registers. + + reg-names: + items: + - const: dwc3_core + - const: host_cfg + - const: usbint_cfg + + interrupts: + items: + - description: Core DWC3 interrupt. + - description: High speed power management event for remote wakeup f= rom hibernation. + - description: Super speed power management event for remote wakeup = from hibernation. + + interrupt-names: + items: + - const: dwc_usb3 + - const: hs_pme + - const: ss_pme + + clocks: + items: + - description: Non-sticky module clock. + - description: Sticky module clock. + - description: USB2 PHY APB clock. + + clock-names: + items: + - const: non_sticky + - const: sticky + - const: u2phy_apb + + resets: + items: + - description: Non-sticky module reset. + - description: Sticky module reset. + - description: USB2 PHY APB reset. + - description: DRD bus reset. + - description: Top-level reset. + + reset-names: + items: + - const: non_sticky + - const: sticky + - const: u2phy_apb + - const: drd_bus + - const: top + + power-domains: + items: + - description: Power switchable domain, the child of top domain. + Turning it on puts the controller into full power state, + turning it off puts the controller into power gated state. + - description: Top domain, the parent of power switchable domain. + Turning it on puts the controller into power gated state, + turning it off completely shuts off the controller. + + power-domain-names: + items: + - const: psw + - const: top + + iommus: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - resets + - reset-names + - power-domains + - power-domain-names + +allOf: + - $ref: snps,dwc3-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + usb@c400000 { + compatible =3D "google,gs5-dwc3"; + reg =3D <0 0x0c400000 0 0xd060>, <0 0x0c450000 0 0x14>, <0 0x= 0c450020 0 0x8>; + reg-names =3D "dwc3_core", "host_cfg", "usbint_cfg"; + interrupts =3D , + , + ; + interrupt-names =3D "dwc_usb3", "hs_pme", "ss_pme"; + clocks =3D <&hsion_usbc_non_sticky_clk>, <&hsion_usbc_sticky_= clk>, + <&hsion_u2phy_apb_clk>; + clock-names =3D "non_sticky", "sticky", "u2phy_apb"; + resets =3D <&hsion_resets_usbc_non_sticky>, <&hsion_resets_usb= c_sticky>, + <&hsion_resets_u2phy_apb>, <&hsion_resets_usb_drd_bus= >, + <&hsion_resets_usb_top>; + reset-names =3D "non_sticky", "sticky", "u2phy_apb", "drd_bus"= , "top"; + power-domains =3D <&hsio_n_usb_psw>, <&hsio_n_usb>; + power-domain-names =3D "psw", "top"; + phys =3D <&usb_phy 0>; + phy-names =3D "usb2-phy"; + snps,quirk-frame-length-adjustment =3D <0x20>; + snps,gfladj-refclk-lpm-sel-quirk; + snps,incr-burst-type-adjustment =3D <4>; + }; + }; +... --=20 2.51.0.740.g6adb054d12-goog