Add a flag indicating whenever ENCLS[EUPDATESVN] SGX instruction is
supported. This will be used by SGX driver to perform CPU SVN updates.
Reviewed-by: Jarkko Sakkinen <jarkko@kernel.org>
Reviewed-by: Kai Huang <kai.huang@intel.com>
Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Elena Reshetova <elena.reshetova@intel.com>
Tested-by: Nataliia Bondarevska <bondarn@google.com>
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/cpu/cpuid-deps.c | 1 +
arch/x86/kernel/cpu/scattered.c | 1 +
tools/arch/x86/include/asm/cpufeatures.h | 1 +
4 files changed, 4 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index b2a562217d3f..44e67dcb915f 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -497,6 +497,7 @@
#define X86_FEATURE_CLEAR_CPU_BUF_VM (21*32+13) /* Clear CPU buffers using VERW before VMRUN */
#define X86_FEATURE_IBPB_EXIT_TO_USER (21*32+14) /* Use IBPB on exit-to-userspace, see VMSCAPE bug */
#define X86_FEATURE_ABMC (21*32+15) /* Assignable Bandwidth Monitoring Counters */
+#define X86_FEATURE_SGX_EUPDATESVN (21*32+16) /* Support for ENCLS[EUPDATESVN] instruction */
/*
* BUG word(s)
diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c
index 46efcbd6afa4..3d9f49ad0efd 100644
--- a/arch/x86/kernel/cpu/cpuid-deps.c
+++ b/arch/x86/kernel/cpu/cpuid-deps.c
@@ -79,6 +79,7 @@ static const struct cpuid_dep cpuid_deps[] = {
{ X86_FEATURE_SGX_LC, X86_FEATURE_SGX },
{ X86_FEATURE_SGX1, X86_FEATURE_SGX },
{ X86_FEATURE_SGX2, X86_FEATURE_SGX1 },
+ { X86_FEATURE_SGX_EUPDATESVN, X86_FEATURE_SGX1 },
{ X86_FEATURE_SGX_EDECCSSA, X86_FEATURE_SGX1 },
{ X86_FEATURE_XFD, X86_FEATURE_XSAVES },
{ X86_FEATURE_XFD, X86_FEATURE_XGETBV1 },
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 4cee6213d667..db42470c244e 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -42,6 +42,7 @@ static const struct cpuid_bit cpuid_bits[] = {
{ X86_FEATURE_PER_THREAD_MBA, CPUID_ECX, 0, 0x00000010, 3 },
{ X86_FEATURE_SGX1, CPUID_EAX, 0, 0x00000012, 0 },
{ X86_FEATURE_SGX2, CPUID_EAX, 1, 0x00000012, 0 },
+ { X86_FEATURE_SGX_EUPDATESVN, CPUID_EAX, 10, 0x00000012, 0 },
{ X86_FEATURE_SGX_EDECCSSA, CPUID_EAX, 11, 0x00000012, 0 },
{ X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 },
{ X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 },
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index 06fc0479a23f..30761c905b7d 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -495,6 +495,7 @@
#define X86_FEATURE_TSA_SQ_NO (21*32+11) /* AMD CPU not vulnerable to TSA-SQ */
#define X86_FEATURE_TSA_L1_NO (21*32+12) /* AMD CPU not vulnerable to TSA-L1 */
#define X86_FEATURE_CLEAR_CPU_BUF_VM (21*32+13) /* Clear CPU buffers using VERW before VMRUN */
+#define X86_FEATURE_SGX_EUPDATESVN (21*32+16) /* Support for ENCLS[EUPDATESVN] instruction */
/*
* BUG word(s)
--
2.45.2On 10/10/25 01:52, Elena Reshetova wrote: > diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h > index 06fc0479a23f..30761c905b7d 100644 > --- a/tools/arch/x86/include/asm/cpufeatures.h > +++ b/tools/arch/x86/include/asm/cpufeatures.h > @@ -495,6 +495,7 @@ > #define X86_FEATURE_TSA_SQ_NO (21*32+11) /* AMD CPU not vulnerable to TSA-SQ */ > #define X86_FEATURE_TSA_L1_NO (21*32+12) /* AMD CPU not vulnerable to TSA-L1 */ > #define X86_FEATURE_CLEAR_CPU_BUF_VM (21*32+13) /* Clear CPU buffers using VERW before VMRUN */ > +#define X86_FEATURE_SGX_EUPDATESVN (21*32+16) /* Support for ENCLS[EUPDATESVN] instruction */ Sorry I didn't catch this before, but we don't patch this tools/ file for individual features. We just sync the main copy over to here from time to time. This hunk needs to die. Second, please don't send things during the merge window. That's both because we're busy, but also because I'm going to merge your code on top of $VERSION-rc1. I'm not sure what you rebased to, but things don't apply cleanly now. Can you please fix the tools/ thing, rebase this on -rc1, retest and resend?
> -----Original Message----- > From: Hansen, Dave <dave.hansen@intel.com> > Sent: Wednesday, October 15, 2025 11:43 PM > To: Reshetova, Elena <elena.reshetova@intel.com> > Cc: jarkko@kernel.org; seanjc@google.com; Huang, Kai > <kai.huang@intel.com>; mingo@kernel.org; linux-sgx@vger.kernel.org; linux- > kernel@vger.kernel.org; x86@kernel.org; Mallick, Asit K > <asit.k.mallick@intel.com>; Scarlata, Vincent R <vincent.r.scarlata@intel.com>; > Cai, Chong <chongc@google.com>; Aktas, Erdem <erdemaktas@google.com>; > Annapurve, Vishal <vannapurve@google.com>; Bondarevska, Nataliia > <bondarn@google.com>; Raynor, Scott <scott.raynor@intel.com>; Dave Hansen > <dave.hansen@linux.intel.com> > Subject: Re: [PATCH v16 2/5] x86/cpufeatures: Add > X86_FEATURE_SGX_EUPDATESVN feature flag > > On 10/10/25 01:52, Elena Reshetova wrote: > > diff --git a/tools/arch/x86/include/asm/cpufeatures.h > b/tools/arch/x86/include/asm/cpufeatures.h > > index 06fc0479a23f..30761c905b7d 100644 > > --- a/tools/arch/x86/include/asm/cpufeatures.h > > +++ b/tools/arch/x86/include/asm/cpufeatures.h > > @@ -495,6 +495,7 @@ > > #define X86_FEATURE_TSA_SQ_NO (21*32+11) /* AMD CPU not > vulnerable to TSA-SQ */ > > #define X86_FEATURE_TSA_L1_NO (21*32+12) /* AMD CPU not > vulnerable to TSA-L1 */ > > #define X86_FEATURE_CLEAR_CPU_BUF_VM (21*32+13) /* Clear CPU > buffers using VERW before VMRUN */ > > +#define X86_FEATURE_SGX_EUPDATESVN (21*32+16) /* Support for > ENCLS[EUPDATESVN] instruction */ > > Sorry I didn't catch this before, but we don't patch this tools/ file > for individual features. We just sync the main copy over to here from > time to time. This hunk needs to die. > > Second, please don't send things during the merge window. That's both > because we're busy, but also because I'm going to merge your code on top > of $VERSION-rc1. I'm not sure what you rebased to, but things don't > apply cleanly now. > > Can you please fix the tools/ thing, rebase this on -rc1, retest and resend? Sure, will do, thanks! Previous version was based on x86_tip/master, will rebase on 6.18-rc1.
On 10/15/25 23:38, Reshetova, Elena wrote: > Sure, will do, thanks! > Previous version was based on x86_tip/master Just FWIW, that means very little. During the merge window it should _mostly_ be gunk that's already gone up for -rc1. But it might also contain cruft that _didn't_ go up and needs another cycle. Please just base things on a tag in Linus's tree unless you have an explicit, known, called-out-in-your-changelog dependency on something in tip. tl;dr: Basing on tip/x86/master was a bug here, not a feature.
> -----Original Message----- > From: Hansen, Dave <dave.hansen@intel.com> > Sent: Friday, October 17, 2025 12:41 AM > To: Reshetova, Elena <elena.reshetova@intel.com> > Cc: jarkko@kernel.org; seanjc@google.com; Huang, Kai > <kai.huang@intel.com>; mingo@kernel.org; linux-sgx@vger.kernel.org; linux- > kernel@vger.kernel.org; x86@kernel.org; Mallick, Asit K > <asit.k.mallick@intel.com>; Scarlata, Vincent R <vincent.r.scarlata@intel.com>; > Cai, Chong <chongc@google.com>; Aktas, Erdem <erdemaktas@google.com>; > Annapurve, Vishal <vannapurve@google.com>; Bondarevska, Nataliia > <bondarn@google.com>; Raynor, Scott <scott.raynor@intel.com>; Dave Hansen > <dave.hansen@linux.intel.com> > Subject: Re: [PATCH v16 2/5] x86/cpufeatures: Add > X86_FEATURE_SGX_EUPDATESVN feature flag > > On 10/15/25 23:38, Reshetova, Elena wrote: > > Sure, will do, thanks! > > Previous version was based on x86_tip/master > > Just FWIW, that means very little. During the merge window it should > _mostly_ be gunk that's already gone up for -rc1. But it might also > contain cruft that _didn't_ go up and needs another cycle. > > Please just base things on a tag in Linus's tree unless you have an > explicit, known, called-out-in-your-changelog dependency on something in > tip. > > tl;dr: Basing on tip/x86/master was a bug here, not a feature. Thank you very much for explaining! I didn’t know how x86_tip is managed, now it is clear also for future. And thank you for pulling the patches in! Best Regards, Elena.
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