From nobody Fri Dec 19 12:15:22 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D72FF26560B; Fri, 10 Oct 2025 08:54:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760086462; cv=none; b=D9I5gLbhd+YlxDu1RtRbthKEyZlOjih1F7sukkbaaFOBlALFsJSPzfwyo+Uj684HSZjvacw4A0b9IwamJps5qAw72Lj2+W+F6imIeyBvXIPui5ohW3FvfJy2NGcsOFf+eztOe9Nq7TVJSm+/K+rHvbN0BXuVYdcDYLkIAHD1suc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760086462; c=relaxed/simple; bh=HPqpeVuYAKFyXYqpap9wjJwZfmxjedJTo0Vp6RHkc0w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dCTJoZl1cR1go841obx7NX92ev9JPNEP2SEt/tpyyLq5dWWCGUqdAsOEfqhbaMdmKZkx6y7Xl87LBXBPzzkRAXFJPI0vWxzeUzPUhnQDbA8e6o7MIJjjsqnwTXPmEebL96+UhE689G54Sxk+8If/3cPEI79NkafWtfNAKsGRW4E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WrlMBX68; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WrlMBX68" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1760086461; x=1791622461; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HPqpeVuYAKFyXYqpap9wjJwZfmxjedJTo0Vp6RHkc0w=; b=WrlMBX68NwsFPEpWl3UUkB0STOHmlutRtlAn3DhTG0wNm5cyyN+4b05+ eKnoNz1iIkojDgJ6fIMTrlKzqZTc6N+mThHs2xGSqIdZ0NOxVlQwUBNoS 2/jk7OqcUtzM+3OZN9q6mR+6dmIH7gQmOFXpT29a3/xR6oScle7piFYgW IDZ3onbYEsbsYJm3nvvKGmSU5X64JPTzRkQONUWh5YUZOilKOvbobXYyF W9RZZKKKM0MnQLRy0tPl2xk4AeWp1odR7XZjaYcg/RsNvGpE/yQmo+tKQ NKpiOesmrA8Fr5VtcuP34zc+FUvCjrYuRkj90XAzP3ekOns8foPmQcK7w w==; X-CSE-ConnectionGUID: 2C4jhoirQ+SmjxCG1B6+xQ== X-CSE-MsgGUID: BwtxO7QCTeytgjyMbJ3iNA== X-IronPort-AV: E=McAfee;i="6800,10657,11577"; a="62188027" X-IronPort-AV: E=Sophos;i="6.19,218,1754982000"; d="scan'208";a="62188027" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2025 01:54:21 -0700 X-CSE-ConnectionGUID: LQbXHCAdSqWwt5HAZt3umQ== X-CSE-MsgGUID: hmVVIfZNSzub52l5leOcig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,218,1754982000"; d="scan'208";a="180181660" Received: from mjarzebo-mobl1.ger.corp.intel.com (HELO eresheto-mobl3.ger.corp.intel.com) ([10.245.245.124]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2025 01:54:15 -0700 From: Elena Reshetova To: dave.hansen@intel.com Cc: jarkko@kernel.org, seanjc@google.com, kai.huang@intel.com, mingo@kernel.org, linux-sgx@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, asit.k.mallick@intel.com, vincent.r.scarlata@intel.com, chongc@google.com, erdemaktas@google.com, vannapurve@google.com, bondarn@google.com, scott.raynor@intel.com, Elena Reshetova , Dave Hansen Subject: [PATCH v16 2/5] x86/cpufeatures: Add X86_FEATURE_SGX_EUPDATESVN feature flag Date: Fri, 10 Oct 2025 11:52:08 +0300 Message-ID: <20251010085346.292287-3-elena.reshetova@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20251010085346.292287-1-elena.reshetova@intel.com> References: <20251010085346.292287-1-elena.reshetova@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a flag indicating whenever ENCLS[EUPDATESVN] SGX instruction is supported. This will be used by SGX driver to perform CPU SVN updates. Reviewed-by: Jarkko Sakkinen Reviewed-by: Kai Huang Reviewed-by: Dave Hansen Signed-off-by: Elena Reshetova Tested-by: Nataliia Bondarevska --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 1 + arch/x86/kernel/cpu/scattered.c | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index b2a562217d3f..44e67dcb915f 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -497,6 +497,7 @@ #define X86_FEATURE_CLEAR_CPU_BUF_VM (21*32+13) /* Clear CPU buffers using= VERW before VMRUN */ #define X86_FEATURE_IBPB_EXIT_TO_USER (21*32+14) /* Use IBPB on exit-to-us= erspace, see VMSCAPE bug */ #define X86_FEATURE_ABMC (21*32+15) /* Assignable Bandwidth Monitoring Co= unters */ +#define X86_FEATURE_SGX_EUPDATESVN (21*32+16) /* Support for ENCLS[EUPDATE= SVN] instruction */ =20 /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index 46efcbd6afa4..3d9f49ad0efd 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -79,6 +79,7 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_SGX_LC, X86_FEATURE_SGX }, { X86_FEATURE_SGX1, X86_FEATURE_SGX }, { X86_FEATURE_SGX2, X86_FEATURE_SGX1 }, + { X86_FEATURE_SGX_EUPDATESVN, X86_FEATURE_SGX1 }, { X86_FEATURE_SGX_EDECCSSA, X86_FEATURE_SGX1 }, { X86_FEATURE_XFD, X86_FEATURE_XSAVES }, { X86_FEATURE_XFD, X86_FEATURE_XGETBV1 }, diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index 4cee6213d667..db42470c244e 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -42,6 +42,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_PER_THREAD_MBA, CPUID_ECX, 0, 0x00000010, 3 }, { X86_FEATURE_SGX1, CPUID_EAX, 0, 0x00000012, 0 }, { X86_FEATURE_SGX2, CPUID_EAX, 1, 0x00000012, 0 }, + { X86_FEATURE_SGX_EUPDATESVN, CPUID_EAX, 10, 0x00000012, 0 }, { X86_FEATURE_SGX_EDECCSSA, CPUID_EAX, 11, 0x00000012, 0 }, { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 }, { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/incl= ude/asm/cpufeatures.h index 06fc0479a23f..30761c905b7d 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -495,6 +495,7 @@ #define X86_FEATURE_TSA_SQ_NO (21*32+11) /* AMD CPU not vulnerable to TSA= -SQ */ #define X86_FEATURE_TSA_L1_NO (21*32+12) /* AMD CPU not vulnerable to TSA= -L1 */ #define X86_FEATURE_CLEAR_CPU_BUF_VM (21*32+13) /* Clear CPU buffers using= VERW before VMRUN */ +#define X86_FEATURE_SGX_EUPDATESVN (21*32+16) /* Support for ENCLS[EUPDATE= SVN] instruction */ =20 /* * BUG word(s) --=20 2.45.2