Document the device tree bindings for the USB PHY interfaces integrated
with the DWC3 controller on Google Tensor SoCs, starting with G5
generation.
Due to a complete architectural overhaul in the Google Tensor G5, the
existing Samsung/Exynos USB PHY driver and binding for older generations
of Google silicons such as gs101 are no longer compatible.
The USB PHY on Tensor G5 includes two integrated Synopsys PHY IPs: the
eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo PHY IP. Currently only
USB high-speed is described and supported.
Signed-off-by: Roy Luo <royluo@google.com>
---
.../bindings/phy/google,gs-usb-phy.yaml | 96 +++++++++++++++++++
1 file changed, 96 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/google,gs-usb-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/google,gs-usb-phy.yaml b/Documentation/devicetree/bindings/phy/google,gs-usb-phy.yaml
new file mode 100644
index 000000000000..22961e2da6ef
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/google,gs-usb-phy.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2025, Google LLC
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/google,gs-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google Tensor Series (G5+) USB PHY
+
+maintainers:
+ - Roy Luo <royluo@google.com>
+
+description: |
+ Describes the USB PHY interfaces integrated with the DWC3 USB controller on
+ Google Tensor SoCs, starting with the G5 generation.
+ Two specific PHY IPs from Synopsys are integrated, including eUSB 2.0 PHY IP
+ and USB 3.2/DisplayPort combo PHY IP.
+ The first phandle argument within the PHY specifier is used to identify the
+ desired PHY. The currently supported value is::
+ 0 - USB high-speed.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - google,gs5-usb-phy
+
+ reg:
+ minItems: 3
+ maxItems: 3
+
+ reg-names:
+ items:
+ - const: usb2_cfg_csr
+ - const: dp_top_csr
+ - const: usb_top_cfg_csr
+
+ "#phy-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: usb2_phy_clk
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: usb2_phy_reset
+
+ power-domains:
+ maxItems: 1
+
+ orientation-switch:
+ type: boolean
+ description:
+ Indicates the PHY as a handler of USB Type-C orientation changes
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#phy-cells"
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ usb_phy: usb_phy@c410000 {
+ compatible = "google,gs5-usb-phy";
+ reg = <0 0x0c450014 0 0xc>,
+ <0 0x0c637000 0 0xa0>,
+ <0 0x0c45002c 0 0x4>;
+ reg-names = "usb2_cfg_csr", "dp_top_csr", "usb_top_cfg_csr";
+ #phy-cells = <1>;
+ clocks = <&hsion_usb2_phy_reset_clk>;
+ clock-names = "usb2_phy_clk";
+ resets = <&hsion_resets_usb2_phy>;
+ reset-names = "usb2_phy_reset";
+ power-domains = <&hsio_n_usb_pd>;
+ orientation-switch;
+ };
+ };
+...
--
2.51.0.710.ga91ca5db03-googOn 08/10/2025 14:59, Roy Luo wrote: > Document the device tree bindings for the USB PHY interfaces integrated > with the DWC3 controller on Google Tensor SoCs, starting with G5 > generation. > > Due to a complete architectural overhaul in the Google Tensor G5, the > existing Samsung/Exynos USB PHY driver and binding for older generations > of Google silicons such as gs101 are no longer compatible. > > The USB PHY on Tensor G5 includes two integrated Synopsys PHY IPs: the > eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo PHY IP. Currently only > USB high-speed is described and supported. > > Signed-off-by: Roy Luo <royluo@google.com> > --- > .../bindings/phy/google,gs-usb-phy.yaml | 96 +++++++++++++++++++ > 1 file changed, 96 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/google,gs-usb-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/google,gs-usb-phy.yaml b/Documentation/devicetree/bindings/phy/google,gs-usb-phy.yaml > new file mode 100644 > index 000000000000..22961e2da6ef > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/google,gs-usb-phy.yaml > @@ -0,0 +1,96 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (C) 2025, Google LLC > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/google,gs-usb-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Google Tensor Series (G5+) USB PHY > + > +maintainers: > + - Roy Luo <royluo@google.com> > + > +description: | > + Describes the USB PHY interfaces integrated with the DWC3 USB controller on > + Google Tensor SoCs, starting with the G5 generation. > + Two specific PHY IPs from Synopsys are integrated, including eUSB 2.0 PHY IP > + and USB 3.2/DisplayPort combo PHY IP. > + The first phandle argument within the PHY specifier is used to identify the > + desired PHY. The currently supported value is:: Currently supported as hardware will change? You describe here hardware ONLY. > + 0 - USB high-speed. > + > +properties: > + compatible: > + items: > + - enum: > + - google,gs5-usb-phy > + > + reg: > + minItems: 3 > + maxItems: 3 > + > + reg-names: > + items: > + - const: usb2_cfg_csr > + - const: dp_top_csr > + - const: usb_top_cfg_csr Drop csr > + > + "#phy-cells": > + const: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + items: > + - const: usb2_phy_clk Drop names, pointless for one entry. > + > + resets: > + maxItems: 1 > + > + reset-names: > + items: > + - const: usb2_phy_reset Drop names, pointless for one entry. > + > + power-domains: > + maxItems: 1 > + > + orientation-switch: > + type: boolean > + description: > + Indicates the PHY as a handler of USB Type-C orientation changes > + > +required: > + - compatible > + - reg > + - reg-names > + - "#phy-cells" > + - clocks > + - clock-names > + - resets > + - reset-names > + > +unevaluatedProperties: false > + additionalProps instead. Read writing schema or example schema. Best regards, Krzysztof
On Wed, Oct 8, 2025 at 4:58 PM Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On 08/10/2025 14:59, Roy Luo wrote: > > Document the device tree bindings for the USB PHY interfaces integrated > > with the DWC3 controller on Google Tensor SoCs, starting with G5 > > generation. > > > > Due to a complete architectural overhaul in the Google Tensor G5, the > > existing Samsung/Exynos USB PHY driver and binding for older generations > > of Google silicons such as gs101 are no longer compatible. > > > > The USB PHY on Tensor G5 includes two integrated Synopsys PHY IPs: the > > eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo PHY IP. Currently only > > USB high-speed is described and supported. > > > > Signed-off-by: Roy Luo <royluo@google.com> > > --- > > .../bindings/phy/google,gs-usb-phy.yaml | 96 +++++++++++++++++++ > > 1 file changed, 96 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/phy/google,gs-usb-phy.yaml > > > > diff --git a/Documentation/devicetree/bindings/phy/google,gs-usb-phy.yaml b/Documentation/devicetree/bindings/phy/google,gs-usb-phy.yaml > > new file mode 100644 > > index 000000000000..22961e2da6ef > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/google,gs-usb-phy.yaml > > @@ -0,0 +1,96 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +# Copyright (C) 2025, Google LLC > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/google,gs-usb-phy.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Google Tensor Series (G5+) USB PHY > > + > > +maintainers: > > + - Roy Luo <royluo@google.com> > > + > > +description: | > > + Describes the USB PHY interfaces integrated with the DWC3 USB controller on > > + Google Tensor SoCs, starting with the G5 generation. > > + Two specific PHY IPs from Synopsys are integrated, including eUSB 2.0 PHY IP > > + and USB 3.2/DisplayPort combo PHY IP. > > + The first phandle argument within the PHY specifier is used to identify the > > + desired PHY. The currently supported value is:: > > Currently supported as hardware will change? You describe here hardware > ONLY. I wanted to explain the PHY specifier as I saw other bindings are also doing it, e.g. "Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml". Theoretically the hardware supports 3 PHY interfaces: high-speed, super-speed and DP, however, the corresponding driver only supports high-speed at the moment. I can still document all the 3 PHY interfaces and assign them with a theoretical specifier value here as that's what the hardware is capable of, and then make it clear that only high-speed is currently supported on the driver side. Does this make sense to you? > > > + 0 - USB high-speed. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - google,gs5-usb-phy > > + > > + reg: > > + minItems: 3 > > + maxItems: 3 > > + > > + reg-names: > > + items: > > + - const: usb2_cfg_csr > > + - const: dp_top_csr > > + - const: usb_top_cfg_csr > > Drop csr > Ack, will fix it in the next patch. > > + > > + "#phy-cells": > > + const: 1 > > + > > + clocks: > > + maxItems: 1 > > + > > + clock-names: > > + items: > > + - const: usb2_phy_clk > > Drop names, pointless for one entry. > Ack, will fix it in the next patch. > > + > > + resets: > > + maxItems: 1 > > + > > + reset-names: > > + items: > > + - const: usb2_phy_reset > > Drop names, pointless for one entry. > Ack, will fix it in the next patch. > > + > > + power-domains: > > + maxItems: 1 > > + > > + orientation-switch: > > + type: boolean > > + description: > > + Indicates the PHY as a handler of USB Type-C orientation changes > > + > > +required: > > + - compatible > > + - reg > > + - reg-names > > + - "#phy-cells" > > + - clocks > > + - clock-names > > + - resets > > + - reset-names > > + > > +unevaluatedProperties: false > > + > > > additionalProps instead. Read writing schema or example schema. > Ack, will fix this in the next patch. Appreciate the review! Thanks, Roy Luo > > Best regards, > Krzysztof
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