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AJvYcCXme4cbBS9aKxD1vuN6R+KaWTYgxyxGWMzErfcMSHlDQ9PNhJrpPxFEYrtGZGmENnqa11uhEcWGX0ZKJWg=@vger.kernel.org X-Gm-Message-State: AOJu0YwP+Yv5usjIrlXsbRhSjl/Kx3s9OV1zCkv/2CDAvwe+Wgfs4++w qAX2AOta2hXVR7CzwoSQY1tXIxwk9uTUGcEoTVj1eQUb1BdWyYaQ8CI7b94RKjDHSfiusLultsb 32x+8WA== X-Google-Smtp-Source: AGHT+IHkVcxa2pum021wuuoLs2okLrcMUb66ABXH6XTGYhxmFAHtMt5/klv2Td06QQp5AMBpCeX1Xhqxjbw= X-Received: from ybbch13.prod.google.com ([2002:a05:6902:b0d:b0:eb5:2c5e:6965]) (user=royluo job=prod-delivery.src-stubby-dispatcher) by 2002:a05:690c:6c08:b0:77f:667f:61f6 with SMTP id 00721157ae682-780e155533dmr45405427b3.15.1759903219488; Tue, 07 Oct 2025 23:00:19 -0700 (PDT) Date: Wed, 8 Oct 2025 05:59:59 +0000 In-Reply-To: <20251008060000.3136021-1-royluo@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251008060000.3136021-1-royluo@google.com> X-Mailer: git-send-email 2.51.0.710.ga91ca5db03-goog Message-ID: <20251008060000.3136021-4-royluo@google.com> Subject: [PATCH v2 3/4] dt-bindings: phy: google: Add Google Tensor G5 USB PHY From: Roy Luo To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Thinh Nguyen , Philipp Zabel , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus Cc: Joy Chakraborty , Naveen Kumar , Roy Luo , Badhri Jagan Sridharan , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the device tree bindings for the USB PHY interfaces integrated with the DWC3 controller on Google Tensor SoCs, starting with G5 generation. Due to a complete architectural overhaul in the Google Tensor G5, the existing Samsung/Exynos USB PHY driver and binding for older generations of Google silicons such as gs101 are no longer compatible. The USB PHY on Tensor G5 includes two integrated Synopsys PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo PHY IP. Currently only USB high-speed is described and supported. Signed-off-by: Roy Luo --- .../bindings/phy/google,gs-usb-phy.yaml | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/google,gs-usb-phy= .yaml diff --git a/Documentation/devicetree/bindings/phy/google,gs-usb-phy.yaml b= /Documentation/devicetree/bindings/phy/google,gs-usb-phy.yaml new file mode 100644 index 000000000000..22961e2da6ef --- /dev/null +++ b/Documentation/devicetree/bindings/phy/google,gs-usb-phy.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2025, Google LLC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/google,gs-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google Tensor Series (G5+) USB PHY + +maintainers: + - Roy Luo + +description: | + Describes the USB PHY interfaces integrated with the DWC3 USB controller= on + Google Tensor SoCs, starting with the G5 generation. + Two specific PHY IPs from Synopsys are integrated, including eUSB 2.0 PH= Y IP + and USB 3.2/DisplayPort combo PHY IP. + The first phandle argument within the PHY specifier is used to identify = the + desired PHY. The currently supported value is:: + 0 - USB high-speed. + +properties: + compatible: + items: + - enum: + - google,gs5-usb-phy + + reg: + minItems: 3 + maxItems: 3 + + reg-names: + items: + - const: usb2_cfg_csr + - const: dp_top_csr + - const: usb_top_cfg_csr + + "#phy-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: usb2_phy_clk + + resets: + maxItems: 1 + + reset-names: + items: + - const: usb2_phy_reset + + power-domains: + maxItems: 1 + + orientation-switch: + type: boolean + description: + Indicates the PHY as a handler of USB Type-C orientation changes + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + - clocks + - clock-names + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + usb_phy: usb_phy@c410000 { + compatible =3D "google,gs5-usb-phy"; + reg =3D <0 0x0c450014 0 0xc>, + <0 0x0c637000 0 0xa0>, + <0 0x0c45002c 0 0x4>; + reg-names =3D "usb2_cfg_csr", "dp_top_csr", "usb_top_cfg_csr"; + #phy-cells =3D <1>; + clocks =3D <&hsion_usb2_phy_reset_clk>; + clock-names =3D "usb2_phy_clk"; + resets =3D <&hsion_resets_usb2_phy>; + reset-names =3D "usb2_phy_reset"; + power-domains =3D <&hsio_n_usb_pd>; + orientation-switch; + }; + }; +... --=20 2.51.0.710.ga91ca5db03-goog