.../clock/amlogic,a4-peripherals-clkc.yaml | 122 +++ .../bindings/clock/amlogic,a4-pll-clkc.yaml | 61 ++ .../clock/amlogic,a5-peripherals-clkc.yaml | 134 ++++ .../bindings/clock/amlogic,a5-pll-clkc.yaml | 63 ++ arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 80 ++ arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 87 ++ drivers/clk/meson/Kconfig | 53 ++ drivers/clk/meson/Makefile | 4 + drivers/clk/meson/a1-pll.c | 1 + drivers/clk/meson/a4-peripherals.c | 764 ++++++++++++++++++ drivers/clk/meson/a4-pll.c | 242 ++++++ drivers/clk/meson/a5-peripherals.c | 883 +++++++++++++++++++++ drivers/clk/meson/a5-pll.c | 476 +++++++++++ drivers/clk/meson/clk-pll.c | 76 +- drivers/clk/meson/clk-pll.h | 2 + .../clock/amlogic,a4-peripherals-clkc.h | 129 +++ include/dt-bindings/clock/amlogic,a4-pll-clkc.h | 15 + include/dt-bindings/clock/amlogic,a4-scmi-clkc.h | 42 + .../clock/amlogic,a5-peripherals-clkc.h | 132 +++ include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 + include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 + 21 files changed, 3406 insertions(+), 28 deletions(-)
This patch series includes changes related to the PLL and peripheral
clocks for both the A4 and A5 SoCs.
The patches for A5 were previously submitted up to V3 by Xianwei.
https://lore.kernel.org/all/20250103-a5-clk-v3-0-a207ce83b9e9@amlogic.com/
After friendly coordination, I’ve taken over and continued the
submission as part of this series. The dt-bindings patch retains Rob's
original "Reviewed-by" tag, and I hope this hasn’t caused any
additional confusion.
Both A4 and A5 belong to the Audio series. Judging by their names, one
might assume that A5 is an upgrade to A4, but in fact, A5 was released
a year earlier than A4.
Since there are differences in the PLLs and peripheral clocks between
the A4 and A5 SoCs (especially the PLL), and taking into account factors
such as memory footprint and maintainability, this series does not
attempt to merge the two into a shared driver as was done for
G12A/G12B/SM1.
This patch series includes all related dt-bindings, driver, and dts
changes for the PLLs and peripheral clocks. Following our past convention
for clock-related submissions, the dts changes are placed at the end
and submitted separately. If this ordering makes it harder for
maintainers to review or pick patches, please feel free to point it out.
Co-developed-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
Chuan Liu (19):
dt-bindings: clock: Add Amlogic A4 SCMI clock controller
dt-bindings: clock: Add Amlogic A4 PLL clock controller
dt-bindings: clock: Add Amlogic A4 peripherals clock controller
clk: amlogic: Optimize PLL enable timing
clk: amlogic: Correct l_detect bit control
clk: amlogic: Fix out-of-range PLL frequency setting
clk: amlogic: Add A4 PLL clock controller driver
clk: amlogic: Add A4 clock peripherals controller driver
arm64: dts: amlogic: A4: Add scmi-clk node
arm64: dts: amlogic: A4: Add PLL controller node
arm64: dts: amlogic: A4: Add peripherals clock controller node
dt-bindings: clock: Add Amlogic A5 SCMI clock controller support
dt-bindings: clock: Add Amlogic A5 PLL clock controller
dt-bindings: clock: Add Amlogic A5 peripherals clock controller
clk: amlogic: Add A5 PLL clock controller driver
clk: amlogic: Add A5 clock peripherals controller driver
arm64: dts: amlogic: A5: Add scmi-clk node
arm64: dts: amlogic: A5: Add PLL controller node
arm64: dts: amlogic: A5: Add peripheral clock controller node
.../clock/amlogic,a4-peripherals-clkc.yaml | 122 +++
.../bindings/clock/amlogic,a4-pll-clkc.yaml | 61 ++
.../clock/amlogic,a5-peripherals-clkc.yaml | 134 ++++
.../bindings/clock/amlogic,a5-pll-clkc.yaml | 63 ++
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 80 ++
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 87 ++
drivers/clk/meson/Kconfig | 53 ++
drivers/clk/meson/Makefile | 4 +
drivers/clk/meson/a1-pll.c | 1 +
drivers/clk/meson/a4-peripherals.c | 764 ++++++++++++++++++
drivers/clk/meson/a4-pll.c | 242 ++++++
drivers/clk/meson/a5-peripherals.c | 883 +++++++++++++++++++++
drivers/clk/meson/a5-pll.c | 476 +++++++++++
drivers/clk/meson/clk-pll.c | 76 +-
drivers/clk/meson/clk-pll.h | 2 +
.../clock/amlogic,a4-peripherals-clkc.h | 129 +++
include/dt-bindings/clock/amlogic,a4-pll-clkc.h | 15 +
include/dt-bindings/clock/amlogic,a4-scmi-clkc.h | 42 +
.../clock/amlogic,a5-peripherals-clkc.h | 132 +++
include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 +
include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 +
21 files changed, 3406 insertions(+), 28 deletions(-)
---
base-commit: 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf
change-id: 20250928-a4_a5_add_clock_driver-2b7c9d695633
Best regards,
--
Chuan Liu <chuan.liu@amlogic.com>
On Tue 30 Sep 2025 at 17:37, Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@kernel.org> wrote: > This patch series includes changes related to the PLL and peripheral > clocks for both the A4 and A5 SoCs. > > The patches for A5 were previously submitted up to V3 by Xianwei. > https://lore.kernel.org/all/20250103-a5-clk-v3-0-a207ce83b9e9@amlogic.com/ > After friendly coordination, I’ve taken over and continued the > submission as part of this series. The dt-bindings patch retains Rob's > original "Reviewed-by" tag, and I hope this hasn’t caused any > additional confusion. ... and yet you restart the versioning of the series making it harder for people to follow that > > Both A4 and A5 belong to the Audio series. Judging by their names, one > might assume that A5 is an upgrade to A4, but in fact, A5 was released > a year earlier than A4. > > Since there are differences in the PLLs and peripheral clocks between > the A4 and A5 SoCs (especially the PLL), and taking into account factors > such as memory footprint and maintainability, this series does not > attempt to merge the two into a shared driver as was done for > G12A/G12B/SM1. ... and we end up with 19 patches series while it could be splitted into manageable series, for each controller of each SoC > > This patch series includes all related dt-bindings, driver, and dts > changes for the PLLs and peripheral clocks. Following our past convention > for clock-related submissions, the dts changes are placed at the end > and submitted separately. If this ordering makes it harder for > maintainers to review or pick patches, please feel free to point it out. > > Co-developed-by: Xianwei Zhao <xianwei.zhao@amlogic.com> > Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> > Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> > --- > Chuan Liu (19): > dt-bindings: clock: Add Amlogic A4 SCMI clock controller > dt-bindings: clock: Add Amlogic A4 PLL clock controller > dt-bindings: clock: Add Amlogic A4 peripherals clock controller > clk: amlogic: Optimize PLL enable timing > clk: amlogic: Correct l_detect bit control > clk: amlogic: Fix out-of-range PLL frequency setting > clk: amlogic: Add A4 PLL clock controller driver > clk: amlogic: Add A4 clock peripherals controller driver > arm64: dts: amlogic: A4: Add scmi-clk node > arm64: dts: amlogic: A4: Add PLL controller node > arm64: dts: amlogic: A4: Add peripherals clock controller node > dt-bindings: clock: Add Amlogic A5 SCMI clock controller support > dt-bindings: clock: Add Amlogic A5 PLL clock controller > dt-bindings: clock: Add Amlogic A5 peripherals clock controller > clk: amlogic: Add A5 PLL clock controller driver > clk: amlogic: Add A5 clock peripherals controller driver > arm64: dts: amlogic: A5: Add scmi-clk node > arm64: dts: amlogic: A5: Add PLL controller node > arm64: dts: amlogic: A5: Add peripheral clock controller node > > .../clock/amlogic,a4-peripherals-clkc.yaml | 122 +++ > .../bindings/clock/amlogic,a4-pll-clkc.yaml | 61 ++ > .../clock/amlogic,a5-peripherals-clkc.yaml | 134 ++++ > .../bindings/clock/amlogic,a5-pll-clkc.yaml | 63 ++ > arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 80 ++ > arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 87 ++ > drivers/clk/meson/Kconfig | 53 ++ > drivers/clk/meson/Makefile | 4 + > drivers/clk/meson/a1-pll.c | 1 + > drivers/clk/meson/a4-peripherals.c | 764 ++++++++++++++++++ > drivers/clk/meson/a4-pll.c | 242 ++++++ > drivers/clk/meson/a5-peripherals.c | 883 +++++++++++++++++++++ > drivers/clk/meson/a5-pll.c | 476 +++++++++++ > drivers/clk/meson/clk-pll.c | 76 +- > drivers/clk/meson/clk-pll.h | 2 + > .../clock/amlogic,a4-peripherals-clkc.h | 129 +++ > include/dt-bindings/clock/amlogic,a4-pll-clkc.h | 15 + > include/dt-bindings/clock/amlogic,a4-scmi-clkc.h | 42 + > .../clock/amlogic,a5-peripherals-clkc.h | 132 +++ > include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 + > include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 + > 21 files changed, 3406 insertions(+), 28 deletions(-) > --- > base-commit: 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf > change-id: 20250928-a4_a5_add_clock_driver-2b7c9d695633 > > Best regards, -- Jerome
Hi Jerome, Thanks for your review, because the national day holidays did not timely feedback. On 10/1/2025 3:45 PM, Jerome Brunet wrote: > [ EXTERNAL EMAIL ] > > On Tue 30 Sep 2025 at 17:37, Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@kernel.org> wrote: > >> This patch series includes changes related to the PLL and peripheral >> clocks for both the A4 and A5 SoCs. >> >> The patches for A5 were previously submitted up to V3 by Xianwei. >> https://lore.kernel.org/all/20250103-a5-clk-v3-0-a207ce83b9e9@amlogic.com/ >> After friendly coordination, I’ve taken over and continued the >> submission as part of this series. The dt-bindings patch retains Rob's >> original "Reviewed-by" tag, and I hope this hasn’t caused any >> additional confusion. > ... and yet you restart the versioning of the series making it harder > for people to follow that Sorry for the inconvenience caused. The main changes compared to the previous version by Xianwei are in the driver part. The dt-bindings part only has minor modifications in [PATCH 14/19]. The driver part has relatively larger changes because it needs to be based on the code base you previously submitted. >> Both A4 and A5 belong to the Audio series. Judging by their names, one >> might assume that A5 is an upgrade to A4, but in fact, A5 was released >> a year earlier than A4. >> >> Since there are differences in the PLLs and peripheral clocks between >> the A4 and A5 SoCs (especially the PLL), and taking into account factors >> such as memory footprint and maintainability, this series does not >> attempt to merge the two into a shared driver as was done for >> G12A/G12B/SM1. > ... and we end up with 19 patches series while it could be splitted into > manageable series, for each controller of each SoC I'm not sure if I understood you correctly. Do you mean that I should split this series of 19 patches into multiple patch series and send them separately? For example: serie 1: A4 SCMI clock controller (dt-bindings) serie 2: A4 PLL clock controller (dt-bindings, driver, dts) serie 3: A4 peripherals clock controller (dt-bindings, driver, dts) ... A5 similarly? >> This patch series includes all related dt-bindings, driver, and dts >> changes for the PLLs and peripheral clocks. Following our past convention >> for clock-related submissions, the dts changes are placed at the end >> and submitted separately. If this ordering makes it harder for >> maintainers to review or pick patches, please feel free to point it out. >> >> Co-developed-by: Xianwei Zhao <xianwei.zhao@amlogic.com> >> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> >> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> >> --- >> Chuan Liu (19): >> dt-bindings: clock: Add Amlogic A4 SCMI clock controller >> dt-bindings: clock: Add Amlogic A4 PLL clock controller >> dt-bindings: clock: Add Amlogic A4 peripherals clock controller >> clk: amlogic: Optimize PLL enable timing >> clk: amlogic: Correct l_detect bit control >> clk: amlogic: Fix out-of-range PLL frequency setting >> clk: amlogic: Add A4 PLL clock controller driver >> clk: amlogic: Add A4 clock peripherals controller driver >> arm64: dts: amlogic: A4: Add scmi-clk node >> arm64: dts: amlogic: A4: Add PLL controller node >> arm64: dts: amlogic: A4: Add peripherals clock controller node >> dt-bindings: clock: Add Amlogic A5 SCMI clock controller support >> dt-bindings: clock: Add Amlogic A5 PLL clock controller >> dt-bindings: clock: Add Amlogic A5 peripherals clock controller >> clk: amlogic: Add A5 PLL clock controller driver >> clk: amlogic: Add A5 clock peripherals controller driver >> arm64: dts: amlogic: A5: Add scmi-clk node >> arm64: dts: amlogic: A5: Add PLL controller node >> arm64: dts: amlogic: A5: Add peripheral clock controller node >> >> .../clock/amlogic,a4-peripherals-clkc.yaml | 122 +++ >> .../bindings/clock/amlogic,a4-pll-clkc.yaml | 61 ++ >> .../clock/amlogic,a5-peripherals-clkc.yaml | 134 ++++ >> .../bindings/clock/amlogic,a5-pll-clkc.yaml | 63 ++ >> arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 80 ++ >> arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 87 ++ >> drivers/clk/meson/Kconfig | 53 ++ >> drivers/clk/meson/Makefile | 4 + >> drivers/clk/meson/a1-pll.c | 1 + >> drivers/clk/meson/a4-peripherals.c | 764 ++++++++++++++++++ >> drivers/clk/meson/a4-pll.c | 242 ++++++ >> drivers/clk/meson/a5-peripherals.c | 883 +++++++++++++++++++++ >> drivers/clk/meson/a5-pll.c | 476 +++++++++++ >> drivers/clk/meson/clk-pll.c | 76 +- >> drivers/clk/meson/clk-pll.h | 2 + >> .../clock/amlogic,a4-peripherals-clkc.h | 129 +++ >> include/dt-bindings/clock/amlogic,a4-pll-clkc.h | 15 + >> include/dt-bindings/clock/amlogic,a4-scmi-clkc.h | 42 + >> .../clock/amlogic,a5-peripherals-clkc.h | 132 +++ >> include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 + >> include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 + >> 21 files changed, 3406 insertions(+), 28 deletions(-) >> --- >> base-commit: 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf >> change-id: 20250928-a4_a5_add_clock_driver-2b7c9d695633 >> >> Best regards, > -- > Jerome
On Thu 09 Oct 2025 at 11:09, Chuan Liu <chuan.liu@amlogic.com> wrote: > Hi Jerome, > > Thanks for your review, because the national day holidays did not > timely feedback. > > > On 10/1/2025 3:45 PM, Jerome Brunet wrote: >> [ EXTERNAL EMAIL ] >> >> On Tue 30 Sep 2025 at 17:37, Chuan Liu via B4 Relay >> <devnull+chuan.liu.amlogic.com@kernel.org> wrote: >> >>> This patch series includes changes related to the PLL and peripheral >>> clocks for both the A4 and A5 SoCs. >>> >>> The patches for A5 were previously submitted up to V3 by Xianwei. >>> https://lore.kernel.org/all/20250103-a5-clk-v3-0-a207ce83b9e9@amlogic.com/ >>> After friendly coordination, I’ve taken over and continued the >>> submission as part of this series. The dt-bindings patch retains Rob's >>> original "Reviewed-by" tag, and I hope this hasn’t caused any >>> additional confusion. >> ... and yet you restart the versioning of the series making it harder >> for people to follow that > > > Sorry for the inconvenience caused. The main changes compared to the > previous version by Xianwei are in the driver part. > > The dt-bindings part only has minor modifications in [PATCH 14/19]. > > The driver part has relatively larger changes because it needs to be > based on the code base you previously submitted. I'm not seeing a justification for the mess introduced and I'm not looking for one to be honest > >>> Both A4 and A5 belong to the Audio series. Judging by their names, one >>> might assume that A5 is an upgrade to A4, but in fact, A5 was released >>> a year earlier than A4. >>> >>> Since there are differences in the PLLs and peripheral clocks between >>> the A4 and A5 SoCs (especially the PLL), and taking into account factors >>> such as memory footprint and maintainability, this series does not >>> attempt to merge the two into a shared driver as was done for >>> G12A/G12B/SM1. >> ... and we end up with 19 patches series while it could be splitted into >> manageable series, for each controller of each SoC > > > I'm not sure if I understood you correctly. > > Do you mean that I should split this series of 19 patches into multiple > patch series and send them separately? For example: > serie 1: A4 SCMI clock controller (dt-bindings) > serie 2: A4 PLL clock controller (dt-bindings, driver, dts) > serie 3: A4 peripherals clock controller (dt-bindings, driver, dts) > ... A5 similarly? Things that do not actually depends on each other or which are not merged through the same tree should not be sent together. There is nothing new here. Same basic reminders on each submission. > > >>> This patch series includes all related dt-bindings, driver, and dts >>> changes for the PLLs and peripheral clocks. Following our past convention >>> for clock-related submissions, the dts changes are placed at the end >>> and submitted separately. If this ordering makes it harder for >>> maintainers to review or pick patches, please feel free to point it out. >>> >>> Co-developed-by: Xianwei Zhao <xianwei.zhao@amlogic.com> >>> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> >>> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> >>> --- >>> Chuan Liu (19): >>> dt-bindings: clock: Add Amlogic A4 SCMI clock controller >>> dt-bindings: clock: Add Amlogic A4 PLL clock controller >>> dt-bindings: clock: Add Amlogic A4 peripherals clock controller >>> clk: amlogic: Optimize PLL enable timing >>> clk: amlogic: Correct l_detect bit control >>> clk: amlogic: Fix out-of-range PLL frequency setting >>> clk: amlogic: Add A4 PLL clock controller driver >>> clk: amlogic: Add A4 clock peripherals controller driver >>> arm64: dts: amlogic: A4: Add scmi-clk node >>> arm64: dts: amlogic: A4: Add PLL controller node >>> arm64: dts: amlogic: A4: Add peripherals clock controller node >>> dt-bindings: clock: Add Amlogic A5 SCMI clock controller support >>> dt-bindings: clock: Add Amlogic A5 PLL clock controller >>> dt-bindings: clock: Add Amlogic A5 peripherals clock controller >>> clk: amlogic: Add A5 PLL clock controller driver >>> clk: amlogic: Add A5 clock peripherals controller driver >>> arm64: dts: amlogic: A5: Add scmi-clk node >>> arm64: dts: amlogic: A5: Add PLL controller node >>> arm64: dts: amlogic: A5: Add peripheral clock controller node >>> >>> .../clock/amlogic,a4-peripherals-clkc.yaml | 122 +++ >>> .../bindings/clock/amlogic,a4-pll-clkc.yaml | 61 ++ >>> .../clock/amlogic,a5-peripherals-clkc.yaml | 134 ++++ >>> .../bindings/clock/amlogic,a5-pll-clkc.yaml | 63 ++ >>> arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 80 ++ >>> arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 87 ++ >>> drivers/clk/meson/Kconfig | 53 ++ >>> drivers/clk/meson/Makefile | 4 + >>> drivers/clk/meson/a1-pll.c | 1 + >>> drivers/clk/meson/a4-peripherals.c | 764 ++++++++++++++++++ >>> drivers/clk/meson/a4-pll.c | 242 ++++++ >>> drivers/clk/meson/a5-peripherals.c | 883 +++++++++++++++++++++ >>> drivers/clk/meson/a5-pll.c | 476 +++++++++++ >>> drivers/clk/meson/clk-pll.c | 76 +- >>> drivers/clk/meson/clk-pll.h | 2 + >>> .../clock/amlogic,a4-peripherals-clkc.h | 129 +++ >>> include/dt-bindings/clock/amlogic,a4-pll-clkc.h | 15 + >>> include/dt-bindings/clock/amlogic,a4-scmi-clkc.h | 42 + >>> .../clock/amlogic,a5-peripherals-clkc.h | 132 +++ >>> include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 + >>> include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 + >>> 21 files changed, 3406 insertions(+), 28 deletions(-) >>> --- >>> base-commit: 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf >>> change-id: 20250928-a4_a5_add_clock_driver-2b7c9d695633 >>> >>> Best regards, >> -- >> Jerome -- Jerome
Hi Jerome, On 10/9/2025 3:59 PM, Jerome Brunet wrote: > [ EXTERNAL EMAIL ] > > On Thu 09 Oct 2025 at 11:09, Chuan Liu <chuan.liu@amlogic.com> wrote: > >> Hi Jerome, >> >> Thanks for your review, because the national day holidays did not >> timely feedback. >> >> >> On 10/1/2025 3:45 PM, Jerome Brunet wrote: >>> [ EXTERNAL EMAIL ] >>> >>> On Tue 30 Sep 2025 at 17:37, Chuan Liu via B4 Relay >>> <devnull+chuan.liu.amlogic.com@kernel.org> wrote: >>> >>>> This patch series includes changes related to the PLL and peripheral >>>> clocks for both the A4 and A5 SoCs. >>>> >>>> The patches for A5 were previously submitted up to V3 by Xianwei. >>>> https://lore.kernel.org/all/20250103-a5-clk-v3-0-a207ce83b9e9@amlogic.com/ >>>> After friendly coordination, I’ve taken over and continued the >>>> submission as part of this series. The dt-bindings patch retains Rob's >>>> original "Reviewed-by" tag, and I hope this hasn’t caused any >>>> additional confusion. >>> ... and yet you restart the versioning of the series making it harder >>> for people to follow that >> >> Sorry for the inconvenience caused. The main changes compared to the >> previous version by Xianwei are in the driver part. >> >> The dt-bindings part only has minor modifications in [PATCH 14/19]. >> >> The driver part has relatively larger changes because it needs to be >> based on the code base you previously submitted. > I'm not seeing a justification for the mess introduced and I'm not > looking for one to be honest Previously, I provided a basic version of the A5 clock driver to Xianwei, and he helped improve it before submitting it. Xianwei has been responsible for upstreaming many of our modules. Since clock drivers require significant effort, I’m sharing the workload by submitting some of the clock-related patches. The three versions previously submitted by Xianwei mainly focused on improving the dt-bindings based on Rob’s feedback. The driver part remained unchanged. The driver part in my current patch series has undergone relatively large modifications to adapt to the latest code base, so comparing it to the previous versions may not be very meaningful. If it's more appropriate for the A5 clock-related patches to continue evolving based on Xianwei's earlier v3 series, please feel free to point it out. I will continue to assist Xianwei in completing the submission of the remaining A5 clock patches. >>>> Both A4 and A5 belong to the Audio series. Judging by their names, one >>>> might assume that A5 is an upgrade to A4, but in fact, A5 was released >>>> a year earlier than A4. >>>> >>>> Since there are differences in the PLLs and peripheral clocks between >>>> the A4 and A5 SoCs (especially the PLL), and taking into account factors >>>> such as memory footprint and maintainability, this series does not >>>> attempt to merge the two into a shared driver as was done for >>>> G12A/G12B/SM1. >>> ... and we end up with 19 patches series while it could be splitted into >>> manageable series, for each controller of each SoC >> >> I'm not sure if I understood you correctly. >> >> Do you mean that I should split this series of 19 patches into multiple >> patch series and send them separately? For example: >> serie 1: A4 SCMI clock controller (dt-bindings) >> serie 2: A4 PLL clock controller (dt-bindings, driver, dts) >> serie 3: A4 peripherals clock controller (dt-bindings, driver, dts) >> ... A5 similarly? > Things that do not actually depends on each other or which are not > merged through the same tree should not be sent together. There is > nothing new here. Same basic reminders on each submission. Sorry, but I'm still not quite sure if I understood you correctly. This series of 19 patches mainly falls into three major categories: * Optimize PLL driver * PLLs and peripherals for A4 * PLLs and peripherals for A5 Are you suggesting that the PLL driver part should be sent as a separate patch series, while the A4 and A5 parts should still follow the previous A5/C3-style submission? >> >>>> This patch series includes all related dt-bindings, driver, and dts >>>> changes for the PLLs and peripheral clocks. Following our past convention >>>> for clock-related submissions, the dts changes are placed at the end >>>> and submitted separately. If this ordering makes it harder for >>>> maintainers to review or pick patches, please feel free to point it out. >>>> >>>> Co-developed-by: Xianwei Zhao <xianwei.zhao@amlogic.com> >>>> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> >>>> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> >>>> --- >>>> Chuan Liu (19): >>>> dt-bindings: clock: Add Amlogic A4 SCMI clock controller >>>> dt-bindings: clock: Add Amlogic A4 PLL clock controller >>>> dt-bindings: clock: Add Amlogic A4 peripherals clock controller >>>> clk: amlogic: Optimize PLL enable timing >>>> clk: amlogic: Correct l_detect bit control >>>> clk: amlogic: Fix out-of-range PLL frequency setting >>>> clk: amlogic: Add A4 PLL clock controller driver >>>> clk: amlogic: Add A4 clock peripherals controller driver >>>> arm64: dts: amlogic: A4: Add scmi-clk node >>>> arm64: dts: amlogic: A4: Add PLL controller node >>>> arm64: dts: amlogic: A4: Add peripherals clock controller node >>>> dt-bindings: clock: Add Amlogic A5 SCMI clock controller support >>>> dt-bindings: clock: Add Amlogic A5 PLL clock controller >>>> dt-bindings: clock: Add Amlogic A5 peripherals clock controller >>>> clk: amlogic: Add A5 PLL clock controller driver >>>> clk: amlogic: Add A5 clock peripherals controller driver >>>> arm64: dts: amlogic: A5: Add scmi-clk node >>>> arm64: dts: amlogic: A5: Add PLL controller node >>>> arm64: dts: amlogic: A5: Add peripheral clock controller node >>>> >>>> .../clock/amlogic,a4-peripherals-clkc.yaml | 122 +++ >>>> .../bindings/clock/amlogic,a4-pll-clkc.yaml | 61 ++ >>>> .../clock/amlogic,a5-peripherals-clkc.yaml | 134 ++++ >>>> .../bindings/clock/amlogic,a5-pll-clkc.yaml | 63 ++ >>>> arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 80 ++ >>>> arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 87 ++ >>>> drivers/clk/meson/Kconfig | 53 ++ >>>> drivers/clk/meson/Makefile | 4 + >>>> drivers/clk/meson/a1-pll.c | 1 + >>>> drivers/clk/meson/a4-peripherals.c | 764 ++++++++++++++++++ >>>> drivers/clk/meson/a4-pll.c | 242 ++++++ >>>> drivers/clk/meson/a5-peripherals.c | 883 +++++++++++++++++++++ >>>> drivers/clk/meson/a5-pll.c | 476 +++++++++++ >>>> drivers/clk/meson/clk-pll.c | 76 +- >>>> drivers/clk/meson/clk-pll.h | 2 + >>>> .../clock/amlogic,a4-peripherals-clkc.h | 129 +++ >>>> include/dt-bindings/clock/amlogic,a4-pll-clkc.h | 15 + >>>> include/dt-bindings/clock/amlogic,a4-scmi-clkc.h | 42 + >>>> .../clock/amlogic,a5-peripherals-clkc.h | 132 +++ >>>> include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 + >>>> include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 + >>>> 21 files changed, 3406 insertions(+), 28 deletions(-) >>>> --- >>>> base-commit: 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf >>>> change-id: 20250928-a4_a5_add_clock_driver-2b7c9d695633 >>>> >>>> Best regards, >>> -- >>> Jerome > -- > Jerome
On 10/10/2025 04:38, Chuan Liu wrote: > Hi Jerome, > > > On 10/9/2025 3:59 PM, Jerome Brunet wrote: >> [ EXTERNAL EMAIL ] >> >> On Thu 09 Oct 2025 at 11:09, Chuan Liu <chuan.liu@amlogic.com> wrote: >> >>> Hi Jerome, >>> >>> Thanks for your review, because the national day holidays did not >>> timely feedback. >>> >>> >>> On 10/1/2025 3:45 PM, Jerome Brunet wrote: >>>> [ EXTERNAL EMAIL ] >>>> >>>> On Tue 30 Sep 2025 at 17:37, Chuan Liu via B4 Relay >>>> <devnull+chuan.liu.amlogic.com@kernel.org> wrote: >>>> >>>>> This patch series includes changes related to the PLL and peripheral >>>>> clocks for both the A4 and A5 SoCs. >>>>> >>>>> The patches for A5 were previously submitted up to V3 by Xianwei. >>>>> https://lore.kernel.org/all/20250103-a5-clk-v3-0-a207ce83b9e9@amlogic.com/ >>>>> After friendly coordination, I’ve taken over and continued the >>>>> submission as part of this series. The dt-bindings patch retains Rob's >>>>> original "Reviewed-by" tag, and I hope this hasn’t caused any >>>>> additional confusion. >>>> ... and yet you restart the versioning of the series making it harder >>>> for people to follow that >>> >>> Sorry for the inconvenience caused. The main changes compared to the >>> previous version by Xianwei are in the driver part. >>> >>> The dt-bindings part only has minor modifications in [PATCH 14/19]. >>> >>> The driver part has relatively larger changes because it needs to be >>> based on the code base you previously submitted. >> I'm not seeing a justification for the mess introduced and I'm not >> looking for one to be honest > > > Previously, I provided a basic version of the A5 clock driver to > Xianwei, and he helped improve it before submitting it. > > Xianwei has been responsible for upstreaming many of our modules. > Since clock drivers require significant effort, I’m sharing the > workload by submitting some of the clock-related patches. > > The three versions previously submitted by Xianwei mainly focused on > improving the dt-bindings based on Rob’s feedback. The driver part > remained unchanged. > > The driver part in my current patch series has undergone relatively > large modifications to adapt to the latest code base, so comparing it > to the previous versions may not be very meaningful. > > If it's more appropriate for the A5 clock-related patches to continue > evolving based on Xianwei's earlier v3 series, please feel free to > point it out. I will continue to assist Xianwei in completing the > submission of the remaining A5 clock patches. > > >>>>> Both A4 and A5 belong to the Audio series. Judging by their names, one >>>>> might assume that A5 is an upgrade to A4, but in fact, A5 was released >>>>> a year earlier than A4. >>>>> >>>>> Since there are differences in the PLLs and peripheral clocks between >>>>> the A4 and A5 SoCs (especially the PLL), and taking into account factors >>>>> such as memory footprint and maintainability, this series does not >>>>> attempt to merge the two into a shared driver as was done for >>>>> G12A/G12B/SM1. >>>> ... and we end up with 19 patches series while it could be splitted into >>>> manageable series, for each controller of each SoC >>> >>> I'm not sure if I understood you correctly. >>> >>> Do you mean that I should split this series of 19 patches into multiple >>> patch series and send them separately? For example: >>> serie 1: A4 SCMI clock controller (dt-bindings) >>> serie 2: A4 PLL clock controller (dt-bindings, driver, dts) >>> serie 3: A4 peripherals clock controller (dt-bindings, driver, dts) >>> ... A5 similarly? >> Things that do not actually depends on each other or which are not >> merged through the same tree should not be sent together. There is >> nothing new here. Same basic reminders on each submission. > > > Sorry, but I'm still not quite sure if I understood you correctly. > > This series of 19 patches mainly falls into three major categories: > * Optimize PLL driver > * PLLs and peripherals for A4 > * PLLs and peripherals for A5 > > Are you suggesting that the PLL driver part should be sent as a > separate patch series, while the A4 and A5 parts should still follow > the previous A5/C3-style submission? > Please read submitting patches, soc maintainer profile and DT submitting patches documents. You ask us to repeat same knowledge multiple times. It's waste of our time, so we have documented it for your convenience. Best regards, Krzysztof
Hi Krzysztof, Sorry for bothering you unintentionally. I haven't fully understood some of the details yet, I'll do my best to work through them. Thanks again for your reminder. On 10/10/2025 10:42 AM, Krzysztof Kozlowski wrote: > [ EXTERNAL EMAIL ] > > On 10/10/2025 04:38, Chuan Liu wrote: >> Hi Jerome, >> >> >> On 10/9/2025 3:59 PM, Jerome Brunet wrote: >>> [ EXTERNAL EMAIL ] >>> >>> On Thu 09 Oct 2025 at 11:09, Chuan Liu <chuan.liu@amlogic.com> wrote: >>> >>>> Hi Jerome, >>>> >>>> Thanks for your review, because the national day holidays did not >>>> timely feedback. >>>> >>>> >>>> On 10/1/2025 3:45 PM, Jerome Brunet wrote: >>>>> [ EXTERNAL EMAIL ] >>>>> >>>>> On Tue 30 Sep 2025 at 17:37, Chuan Liu via B4 Relay >>>>> <devnull+chuan.liu.amlogic.com@kernel.org> wrote: >>>>> >>>>>> This patch series includes changes related to the PLL and peripheral >>>>>> clocks for both the A4 and A5 SoCs. >>>>>> >>>>>> The patches for A5 were previously submitted up to V3 by Xianwei. >>>>>> https://lore.kernel.org/all/20250103-a5-clk-v3-0-a207ce83b9e9@amlogic.com/ >>>>>> After friendly coordination, I’ve taken over and continued the >>>>>> submission as part of this series. The dt-bindings patch retains Rob's >>>>>> original "Reviewed-by" tag, and I hope this hasn’t caused any >>>>>> additional confusion. >>>>> ... and yet you restart the versioning of the series making it harder >>>>> for people to follow that >>>> >>>> Sorry for the inconvenience caused. The main changes compared to the >>>> previous version by Xianwei are in the driver part. >>>> >>>> The dt-bindings part only has minor modifications in [PATCH 14/19]. >>>> >>>> The driver part has relatively larger changes because it needs to be >>>> based on the code base you previously submitted. >>> I'm not seeing a justification for the mess introduced and I'm not >>> looking for one to be honest >> >> >> Previously, I provided a basic version of the A5 clock driver to >> Xianwei, and he helped improve it before submitting it. >> >> Xianwei has been responsible for upstreaming many of our modules. >> Since clock drivers require significant effort, I’m sharing the >> workload by submitting some of the clock-related patches. >> >> The three versions previously submitted by Xianwei mainly focused on >> improving the dt-bindings based on Rob’s feedback. The driver part >> remained unchanged. >> >> The driver part in my current patch series has undergone relatively >> large modifications to adapt to the latest code base, so comparing it >> to the previous versions may not be very meaningful. >> >> If it's more appropriate for the A5 clock-related patches to continue >> evolving based on Xianwei's earlier v3 series, please feel free to >> point it out. I will continue to assist Xianwei in completing the >> submission of the remaining A5 clock patches. >> >> >>>>>> Both A4 and A5 belong to the Audio series. Judging by their names, one >>>>>> might assume that A5 is an upgrade to A4, but in fact, A5 was released >>>>>> a year earlier than A4. >>>>>> >>>>>> Since there are differences in the PLLs and peripheral clocks between >>>>>> the A4 and A5 SoCs (especially the PLL), and taking into account factors >>>>>> such as memory footprint and maintainability, this series does not >>>>>> attempt to merge the two into a shared driver as was done for >>>>>> G12A/G12B/SM1. >>>>> ... and we end up with 19 patches series while it could be splitted into >>>>> manageable series, for each controller of each SoC >>>> >>>> I'm not sure if I understood you correctly. >>>> >>>> Do you mean that I should split this series of 19 patches into multiple >>>> patch series and send them separately? For example: >>>> serie 1: A4 SCMI clock controller (dt-bindings) >>>> serie 2: A4 PLL clock controller (dt-bindings, driver, dts) >>>> serie 3: A4 peripherals clock controller (dt-bindings, driver, dts) >>>> ... A5 similarly? >>> Things that do not actually depends on each other or which are not >>> merged through the same tree should not be sent together. There is >>> nothing new here. Same basic reminders on each submission. >> >> >> Sorry, but I'm still not quite sure if I understood you correctly. >> >> This series of 19 patches mainly falls into three major categories: >> * Optimize PLL driver >> * PLLs and peripherals for A4 >> * PLLs and peripherals for A5 >> >> Are you suggesting that the PLL driver part should be sent as a >> separate patch series, while the A4 and A5 parts should still follow >> the previous A5/C3-style submission? >> > > Please read submitting patches, soc maintainer profile and DT submitting > patches documents. You ask us to repeat same knowledge multiple times. > It's waste of our time, so we have documented it for your convenience. > > Best regards, > Krzysztof
On Tue, 30 Sep 2025 17:37:13 +0800, Chuan Liu wrote: > This patch series includes changes related to the PLL and peripheral > clocks for both the A4 and A5 SoCs. > > The patches for A5 were previously submitted up to V3 by Xianwei. > https://lore.kernel.org/all/20250103-a5-clk-v3-0-a207ce83b9e9@amlogic.com/ > After friendly coordination, I’ve taken over and continued the > submission as part of this series. The dt-bindings patch retains Rob's > original "Reviewed-by" tag, and I hope this hasn’t caused any > additional confusion. > > Both A4 and A5 belong to the Audio series. Judging by their names, one > might assume that A5 is an upgrade to A4, but in fact, A5 was released > a year earlier than A4. > > Since there are differences in the PLLs and peripheral clocks between > the A4 and A5 SoCs (especially the PLL), and taking into account factors > such as memory footprint and maintainability, this series does not > attempt to merge the two into a shared driver as was done for > G12A/G12B/SM1. > > This patch series includes all related dt-bindings, driver, and dts > changes for the PLLs and peripheral clocks. Following our past convention > for clock-related submissions, the dts changes are placed at the end > and submitted separately. If this ordering makes it harder for > maintainers to review or pick patches, please feel free to point it out. > > Co-developed-by: Xianwei Zhao <xianwei.zhao@amlogic.com> > Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> > Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> > --- > Chuan Liu (19): > dt-bindings: clock: Add Amlogic A4 SCMI clock controller > dt-bindings: clock: Add Amlogic A4 PLL clock controller > dt-bindings: clock: Add Amlogic A4 peripherals clock controller > clk: amlogic: Optimize PLL enable timing > clk: amlogic: Correct l_detect bit control > clk: amlogic: Fix out-of-range PLL frequency setting > clk: amlogic: Add A4 PLL clock controller driver > clk: amlogic: Add A4 clock peripherals controller driver > arm64: dts: amlogic: A4: Add scmi-clk node > arm64: dts: amlogic: A4: Add PLL controller node > arm64: dts: amlogic: A4: Add peripherals clock controller node > dt-bindings: clock: Add Amlogic A5 SCMI clock controller support > dt-bindings: clock: Add Amlogic A5 PLL clock controller > dt-bindings: clock: Add Amlogic A5 peripherals clock controller > clk: amlogic: Add A5 PLL clock controller driver > clk: amlogic: Add A5 clock peripherals controller driver > arm64: dts: amlogic: A5: Add scmi-clk node > arm64: dts: amlogic: A5: Add PLL controller node > arm64: dts: amlogic: A5: Add peripheral clock controller node > > .../clock/amlogic,a4-peripherals-clkc.yaml | 122 +++ > .../bindings/clock/amlogic,a4-pll-clkc.yaml | 61 ++ > .../clock/amlogic,a5-peripherals-clkc.yaml | 134 ++++ > .../bindings/clock/amlogic,a5-pll-clkc.yaml | 63 ++ > arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 80 ++ > arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 87 ++ > drivers/clk/meson/Kconfig | 53 ++ > drivers/clk/meson/Makefile | 4 + > drivers/clk/meson/a1-pll.c | 1 + > drivers/clk/meson/a4-peripherals.c | 764 ++++++++++++++++++ > drivers/clk/meson/a4-pll.c | 242 ++++++ > drivers/clk/meson/a5-peripherals.c | 883 +++++++++++++++++++++ > drivers/clk/meson/a5-pll.c | 476 +++++++++++ > drivers/clk/meson/clk-pll.c | 76 +- > drivers/clk/meson/clk-pll.h | 2 + > .../clock/amlogic,a4-peripherals-clkc.h | 129 +++ > include/dt-bindings/clock/amlogic,a4-pll-clkc.h | 15 + > include/dt-bindings/clock/amlogic,a4-scmi-clkc.h | 42 + > .../clock/amlogic,a5-peripherals-clkc.h | 132 +++ > include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 + > include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 + > 21 files changed, 3406 insertions(+), 28 deletions(-) > --- > base-commit: 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf > change-id: 20250928-a4_a5_add_clock_driver-2b7c9d695633 > > Best regards, > -- > Chuan Liu <chuan.liu@amlogic.com> > > > My bot found new DTB warnings on the .dts files added or changed in this series. Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments. If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date: pip3 install dtschema --upgrade This patch series was applied (using b4) to base: Base: using specified base-commit 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf If this is not the correct base, please add 'base-commit' tag (or use b4 which does this automatically) New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/amlogic/' for 20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com: Error: arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi:119.19-20 syntax error FATAL ERROR: Unable to parse input tree make[3]: *** [scripts/Makefile.dtbs:131: arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dtb] Error 1 make[2]: *** [scripts/Makefile.build:556: arch/arm64/boot/dts/amlogic] Error 2 make[2]: Target 'arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dtb' not remade because of errors. make[1]: *** [/home/rob/proj/linux-dt-testing/Makefile:1480: amlogic/amlogic-a4-a113l2-ba400.dtb] Error 2 make: *** [Makefile:248: __sub-make] Error 2 make: Target 'amlogic/meson-gxl-s905x-hwacom-amazetv.dtb' not remade because of errors. make: Target 'amlogic/meson-gxl-s905d-sml5442tw.dtb' not remade because of errors. make: Target 'amlogic/meson-gxl-s905d-phicomm-n1.dtb' not remade because of errors. make: Target 'amlogic/meson-s4-s805x2-aq222.dtb' not remade because of errors. make: Target 'amlogic/meson-gxl-s905w-p281.dtb' not remade because of errors. make: Target 'amlogic/meson-gxm-s912-libretech-pc.dtb' not remade because of errors. make: Target 'amlogic/meson-g12a-sei510.dtb' not remade because of errors. make: Target 'amlogic/meson-gxm-q200.dtb' not remade because of errors. make: Target 'amlogic/meson-gxl-s905x-khadas-vim.dtb' not remade because of errors. make: Target 'amlogic/meson-gxlx-s905l-p271.dtb' not remade because of errors. make: Target 'amlogic/meson-gxm-mecool-kiii-pro.dtb' not remade because of errors. make: Target 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'amlogic/meson-gxl-s905d-vero4k-plus.dtb' not remade because of errors. make: Target 'amlogic/meson-sm1-h96-max.dtb' not remade because of errors. make: Target 'amlogic/meson-g12b-bananapi-cm4-mnt-reform2.dtb' not remade because of errors. make: Target 'amlogic/meson-gxl-s905x-p212.dtb' not remade because of errors. make: Target 'amlogic/meson-a1-ad401.dtb' not remade because of errors. make: Target 'amlogic/meson-g12b-odroid-go-ultra.dtb' not remade because of errors. make: Target 'amlogic/meson-g12b-radxa-zero2.dtb' not remade because of errors. make: Target 'amlogic/meson-sm1-x96-air-gbit.dtb' not remade because of errors. make: Target 'amlogic/meson-g12b-dreambox-two.dtb' not remade because of errors. make: Target 'amlogic/meson-sm1-bananapi-m5.dtb' not remade because of errors. make: Target 'amlogic/meson-g12a-u200.dtb' not remade because of errors. make: Target 'amlogic/meson-gxm-rbox-pro.dtb' not remade because of errors. make: Target 'amlogic/meson-gxbb-p201.dtb' not remade because of errors. make: Target 'amlogic/meson-sm1-a95xf3-air.dtb' not remade because of errors. make: Target 'amlogic/amlogic-a4-a113l2-ba400.dtb' not remade because of errors. make: Target 'amlogic/meson-gxl-s805y-xiaomi-aquaman.dtb' not remade because of errors. make: Target 'amlogic/meson-sm1-bananapi-m2-pro.dtb' not remade because of errors. make: Target 'amlogic/meson-gxbb-p200.dtb' not remade because of errors. make: Target 'amlogic/meson-sm1-odroid-c4.dtb' not remade because of errors. make: Target 'amlogic/meson-g12b-s922x-bananapi-m2s.dtb' not remade because of errors. make: Target 'amlogic/meson-sm1-sei610.dtb' not remade because of errors. make: Target 'amlogic/meson-sm1-odroid-hc4.dtb' not remade because of errors. make: Target 'amlogic/meson-g12b-odroid-n2l.dtb' not remade because of errors. make: Target 'amlogic/meson-gxl-s905x-libretech-cc.dtb' not remade because of errors. make: Target 'amlogic/amlogic-c3-c302x-aw409.dtb' not remade because of errors. make: Target 'amlogic/meson-gxl-s905x-nexbox-a95x.dtb' not remade because of errors. make: Target 'amlogic/meson-g12b-a311d-libretech-cc.dtb' not remade because of errors. make: Target 'amlogic/amlogic-t7-a311d2-khadas-vim4.dtb' not remade because of errors. make: Target 'amlogic/meson-gxl-s905w-jethome-jethub-j80.dtb' not remade because of errors. make: Target 'amlogic/meson-sm1-s905d3-libretech-cc.dtb' not remade because of errors. make: Target 'amlogic/amlogic-a5-a113x2-av400.dtb' not remade because of errors. make: Target 'amlogic/meson-gxbb-wetek-hub.dtb' not remade because of errors. make: Target 'amlogic/meson-g12b-s922x-khadas-vim3.dtb' not remade because of errors. make: Target 'amlogic/amlogic-s6-s905x5-bl209.dtb' not remade because of errors. make: Target 'amlogic/amlogic-t7-a311d2-an400.dtb' not remade because of errors. make: Target 'amlogic/meson-gxbb-kii-pro.dtb' not remade because of errors. make: Target 'amlogic/meson-g12b-odroid-n2.dtb' not remade because of errors. make: Target 'amlogic/meson-a1-ad402.dtb' not remade because of errors. make: Target 'amlogic/meson-gxbb-nexbox-a95x.dtb' not remade because of errors. make: Target 'amlogic/meson-axg-jethome-jethub-j110-rev-3.dtb' not remade because of errors. make: Target 'amlogic/amlogic-s7-s805x3-bp201.dtb' not remade because of errors. make: Target 'amlogic/meson-g12b-odroid-n2-plus.dtb' not remade because of errors. make: Target 'amlogic/meson-g12b-gtking-pro.dtb' not remade because of errors. make: Target 'amlogic/meson-g12b-ugoos-am6.dtb' not remade because of errors. make: Target 'amlogic/meson-gxl-s805x-p241.dtb' not remade because of errors. make: Target 'amlogic/meson-g12b-gtking.dtb' not remade because of errors. make: Target 'amlogic/meson-gxbb-nanopi-k2.dtb' not remade because of errors.
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