From nobody Wed Dec 17 14:13:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B92642F533A; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225051; cv=none; b=p59AIGxwiiMtbiNuzw9z/OEgFoNec9owqB87dn6vJpCSCHLKq35EiudL9KuDuwZVKVyOhScKTHebg/xRiU8E8U/CEaqKKWP/yV0dgqeQxOzhIYxNY1wFxtggTyVScv1smnhnFjPgrcF8691rfihlAU/Gf+1PxHQ+ejyHQNqfkAU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225051; c=relaxed/simple; bh=tvbsNP2qVU1cS/ayMypPvum2ysqLXXw2xrupi3Us5z4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FjlsNI7a5eqWRm8Jvk3poTCeDLGmCMXVpB7G89N5axR8qLyy/yddEQ787vAfgsrBP/AdcCtMS0EOzqXgUYkE9aQlBbrVQHDKxoeRcDS9afDUYXSJ5ghw/yTcYmhEnH2wgi225fPoFcbadc7v2uVCZu3MSrM3HVLWF2nt56Erb7Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rr6/GDpa; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rr6/GDpa" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4F585C113D0; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225051; bh=tvbsNP2qVU1cS/ayMypPvum2ysqLXXw2xrupi3Us5z4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=rr6/GDpauEY2HHAqRcDmiTNhPC7TN9DAYYCycVXlDHtgTxBjCkc0uJgP65l+B+keg IG5OhTR5p2myHJndvJuwe6EBdnrjZG+N3ZocVpjpthu4fDFCEKSIhqnL0tv99g9Z3f /V4WdCoMcyEn11g12Y7Dmojcrfqdi5QKtD7H/QqDqdPPB3elrqmiIhYMOcG76ao0z9 /eT1wpxwfTl3tvjwkyJwiUWcYNPXbRbeqkNYAiifZ7b8iIdE14ORShYP/+C9deIr4Y Dpj5k0HogW95ceGK2HuPd2zss+gv7edzgvwTBJ8qWqbvCT8eVyCL68ADpgGTBa2DVf cOxoDpwD8M2vA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41289CAC5B8; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:14 +0800 Subject: [PATCH 01/19] dt-bindings: clock: Add Amlogic A4 SCMI clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-a4_a5_add_clock_driver-v1-1-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=1814; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=lepg6iT8bmM81rEU5ToL/dWT4QLnpMs52RztUgBBpJI=; b=9DlKusjYS9lvJ5c+yIorherlGXVHoEWA7WXl+kn4Crs79ES3JyMECgX8nYfKzxnBZ3aewWJbC PNqO/UxUUyuC5w6Rvv8v4ryBepX5x7v5MVHuUbUJjfzWlvDFRb2nrux X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the SCMI clock controller dt-bindings for Amlogic A4 SoC family. Signed-off-by: Chuan Liu Reviewed-by: Rob Herring (Arm) --- include/dt-bindings/clock/amlogic,a4-scmi-clkc.h | 42 ++++++++++++++++++++= ++++ 1 file changed, 42 insertions(+) diff --git a/include/dt-bindings/clock/amlogic,a4-scmi-clkc.h b/include/dt-= bindings/clock/amlogic,a4-scmi-clkc.h new file mode 100644 index 000000000000..454e492f8f6f --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a4-scmi-clkc.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2025 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu + */ + +#ifndef __AMLOGIC_A4_SCMI_CLKC_H +#define __AMLOGIC_A4_SCMI_CLKC_H + +#define CLKID_OSC 0 +#define CLKID_SYS_CLK 1 +#define CLKID_AXI_CLK 2 +#define CLKID_CPU_CLK 3 +#define CLKID_FIXED_PLL 4 +#define CLKID_GP1_PLL 5 +#define CLKID_ACLKM 6 +#define CLKID_SYS_PLL_DIV16 7 +#define CLKID_CPU_CLK_DIV16 8 +#define CLKID_FCLK_50M_PREDIV 9 +#define CLKID_FCLK_50M_DIV 10 +#define CLKID_FCLK_50M 11 +#define CLKID_FCLK_DIV2_DIV 12 +#define CLKID_FCLK_DIV2 13 +#define CLKID_FCLK_DIV2P5_DIV 14 +#define CLKID_FCLK_DIV2P5 15 +#define CLKID_FCLK_DIV3_DIV 16 +#define CLKID_FCLK_DIV3 17 +#define CLKID_FCLK_DIV4_DIV 18 +#define CLKID_FCLK_DIV4 19 +#define CLKID_FCLK_DIV5_DIV 20 +#define CLKID_FCLK_DIV5 21 +#define CLKID_FCLK_DIV7_DIV 22 +#define CLKID_FCLK_DIV7 23 +#define CLKID_SYS_MMC_PCLK 24 +#define CLKID_SYS_CPU_CTRL 25 +#define CLKID_SYS_IRQ_CTRL 26 +#define CLKID_SYS_GIC 27 +#define CLKID_SYS_BIG_NIC 28 +#define CLKID_AXI_SYS_NIC 29 +#define CLKID_AXI_CPU_DMC 30 + +#endif /* __AMLOGIC_A4_SCMI_CLKC_H */ --=20 2.42.0 From nobody Wed Dec 17 14:13:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B91F22F5333; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225051; cv=none; b=YiY7fppCtcPmEiRQ3nKVQXk+vjJdxv7Yt+S+BzUnCxrcP8pwOvK0FuovactPB64WDqi3qlHCSUuxzCFSm6Vhg4Pxvtnp7TnOiwG/dA9XM4mDSRzsfqeAS0U0e7mY+0Ip+/wRF0QHcdjz2X2G8ErO0KkUl/Acmmaqy0IbNOAIIDU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225051; c=relaxed/simple; bh=Ln6ckunYF1rhHX/pMi0GZqFO1vw1cbwS0hhp7CdYdMQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kLWotdpB4D/2hG7iPaDEAtGJDluqt9/NaOZOMhVkOlqFCm9nDqAyHFJvCU3ow7l2z7ZOW5HRn3rfCDo+OORfh7sa2unyHee/Ft1w8R96siv0qQYMQue01rXUR4qCsy8CpUYbUDg7jbur0SFtrsfFyt6qzIoltDXmZ76n7TYhv2Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=O2YMv6mb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="O2YMv6mb" Received: by smtp.kernel.org (Postfix) with ESMTPS id 645D0C4AF0C; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225051; bh=Ln6ckunYF1rhHX/pMi0GZqFO1vw1cbwS0hhp7CdYdMQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=O2YMv6mbgT79WBGL2LXGTHx37t3nbjWEkdBv8EjwFiEyXCMERsfnMFP+jM7O9BH4M hHOpXyWAVr+LAKZ9ayK7LtVizPGDADJ45BNEnEyhUChIBBn8BD7T9wP0vkv9MBDTFy SbpQ6RnqK4PHEMaQZWpJL5AOYWK1wTuylb4gzMg0/lm9luJJKkQK3Q/9NasUqqbBYP QAeWG37tQYSsq5hWJGrvip2kh5AJ6qSobxFsjWSarOW1weWrp9l8KLEM7zipwdxijk dYj2afvD1CHfI58mk4/7TSoYAic9U1BAPRa3zp/JfMQgROWlCuefoPWuDk3b8i96cB EEmH4GlmuDuew== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F978CAC5B9; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:15 +0800 Subject: [PATCH 02/19] dt-bindings: clock: Add Amlogic A4 PLL clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-a4_a5_add_clock_driver-v1-2-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=2798; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=Ft6yNqo0TZ3QMKb3Jm5Wur9+935/1unmm660KRVPRPE=; b=2dpRYtAPCMjQbgEd7EMDfUTMrfRTEis8Y4GdAn4NjLc4KD01/8j89KXgL4Txe0Cy3rKTBvv3o eLsPuSQ6X+GBUiNTGLkXxVH9r6bIYzfxMxgIszPdqOkuCly5YWFwrHs X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the PLL clock controller dt-bindings for Amlogic A4 SoC family. Signed-off-by: Chuan Liu Reviewed-by: Rob Herring (Arm) --- .../bindings/clock/amlogic,a4-pll-clkc.yaml | 61 ++++++++++++++++++= ++++ include/dt-bindings/clock/amlogic,a4-pll-clkc.h | 15 ++++++ 2 files changed, 76 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,a4-pll-clkc.ya= ml b/Documentation/devicetree/bindings/clock/amlogic,a4-pll-clkc.yaml new file mode 100644 index 000000000000..dafad7bd4407 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a4-pll-clkc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2025 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,a4-pll-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A4 series PLL Clock Controller + +maintainers: + - Neil Armstrong + - Jerome Brunet + - Chuan Liu + - Xianwei Zhao + +properties: + compatible: + const: amlogic,a4-pll-clkc + + reg: + maxItems: 1 + + clocks: + items: + - description: input oscillator + - description: input fix pll + + clock-names: + items: + - const: xtal + - const: fix + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include + apb { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@8000 { + compatible =3D "amlogic,a4-pll-clkc"; + reg =3D <0x0 0x8000 0x0 0x110>; + clocks =3D <&xtal>, + <&scmi_clk CLKID_FIXED_PLL>; + clock-names =3D "xtal", + "fix"; + #clock-cells =3D <1>; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,a4-pll-clkc.h b/include/dt-b= indings/clock/amlogic,a4-pll-clkc.h new file mode 100644 index 000000000000..0950dcd68e0a --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a4-pll-clkc.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2025 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu + */ + +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_A4_PLL_CLKC_H +#define _DT_BINDINGS_CLOCK_AMLOGIC_A4_PLL_CLKC_H + +#define CLKID_GP0_PLL_DCO 0 +#define CLKID_GP0_PLL 1 +#define CLKID_HIFI_PLL_DCO 2 +#define CLKID_HIFI_PLL 3 + +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_A4_PLL_CLKC_H */ --=20 2.42.0 From nobody Wed Dec 17 14:13:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B90A12F39B4; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225051; cv=none; b=U4rjZAe/Xlr4+jfkFUKwK8EOSyRqD8CS6J/Bd1bX3+l73FSr+qLVASIsIq1OiZpCff3HYX+YQg8uYswEzBQZi0P4k/LjAHDBtEPkTHlCUKZOm9jJlHXmgzAtA7fs6XUZqdYQ9CwuP25ycO3VWBUkJIKqqmCz+gnFj5cc3G5a6NA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225051; c=relaxed/simple; bh=hhzYEfgfZJNiOina++Jm2EzVehDXlsbevAJCQFuj9kw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=D4YuUsITr1L7JnP4S+qRHhagw8w5VZJ+8ZHqfEWsdIDMFc/EdPAxs+4cMgqbASl/zqbOSKnJex9pH2Y6B+CGavgJh8mT/zPb07GJ/4jejwtWTUI7dt8YKqO9tPDRMu0mhMsWJuGJBXUXyA5iXFE46psZEn2GX6+0QDFGsJAqjJ8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QV+QzIhw; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QV+QzIhw" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6DA97C16AAE; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225051; bh=hhzYEfgfZJNiOina++Jm2EzVehDXlsbevAJCQFuj9kw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=QV+QzIhwZrE9VWAn6cwpBhVNLO/omJpozHuuNF4t3foc9yGrhmww5m/QgJWNv46S7 rOwkTW6m6RalpsxD+50dKPZENVbPYbXjABCq6w7dOZkbDX9wEvkuh4dd2/9e4KfdOi xaJ6Rl+2nsyjzWEDToS9EhRdsQ9V54QNJco2BZaYVRuYbTeaaoqi/B5r1ifpe8jEVX RkmKU06WgR1gSWqDR0XUeFXDEPFADzkZdzxaf3DesJEW+O6Fo7Piy9+t9srYoNjKng 0jiI14TA10kR4GUdT/b3FlnViUk4XsDJDRDzQIrhuvIJ/ll0EqCmLh351kCX8jfk8A NSlbUBozJZM2A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60DDACCA46F; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:16 +0800 Subject: [PATCH 03/19] dt-bindings: clock: Add Amlogic A4 peripherals clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-a4_a5_add_clock_driver-v1-3-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=8947; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=lhJQX8qWsm+to1dG1JwM0xsIMHODJaKrrUgF0nVZFEY=; b=a7biYnhSuewY3g4iaR1DNoe8YbJFpvLqMwcKYqq5x7ygHLg2BhDtZVK2b441lwLevreswCWx3 Iz8zpdGdPw6BGIliV1Xl1LqVXp8sp8uHulLQ+vnniGCGaRvbBdLTOaO X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the peripherals clock controller dt-bindings for the Amlogic A4 SoC family. Signed-off-by: Chuan Liu Reviewed-by: Rob Herring (Arm) --- .../clock/amlogic,a4-peripherals-clkc.yaml | 122 +++++++++++++++++= ++ .../clock/amlogic,a4-peripherals-clkc.h | 129 +++++++++++++++++= ++++ 2 files changed, 251 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,a4-peripherals= -clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a4-peripherals= -clkc.yaml new file mode 100644 index 000000000000..13a0622f1f64 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a4-peripherals-clkc.y= aml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2025 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,a4-peripherals-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A4 series Peripheral Clock Controller + +maintainers: + - Neil Armstrong + - Jerome Brunet + - Xianwei Zhao + - Chuan Liu + +properties: + compatible: + const: amlogic,a4-peripherals-clkc + + reg: + maxItems: 1 + + clocks: + minItems: 16 + items: + - description: input oscillator + - description: input oscillators multiplexer + - description: input fix pll + - description: input fclk div 2 + - description: input fclk div 2p5 + - description: input fclk div 3 + - description: input fclk div 4 + - description: input fclk div 5 + - description: input fclk div 7 + - description: input gp0 pll + - description: input gp1 pll + - description: input hifi pll + - description: input sys clk + - description: input axi clk + - description: input sys pll div 16 + - description: input cpu clk div 16 + - description: input pad clock for rtc clk (optional) + + clock-names: + minItems: 16 + items: + - const: xtal + - const: oscin + - const: fix + - const: fdiv2 + - const: fdiv2p5 + - const: fdiv3 + - const: fdiv4 + - const: fdiv5 + - const: fdiv7 + - const: gp0 + - const: gp1 + - const: hifi + - const: sysclk + - const: axiclk + - const: sysplldiv16 + - const: cpudiv16 + - const: pad_osc + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include + #include + apb { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@0 { + compatible =3D "amlogic,a4-peripherals-clkc"; + reg =3D <0x0 0x0 0x0 0x20c>; + #clock-cells =3D <1>; + clocks =3D <&xtal>, + <&scmi_clk CLKID_OSC>, + <&scmi_clk CLKID_FIXED_PLL>, + <&scmi_clk CLKID_FCLK_DIV2>, + <&scmi_clk CLKID_FCLK_DIV2P5>, + <&scmi_clk CLKID_FCLK_DIV3>, + <&scmi_clk CLKID_FCLK_DIV4>, + <&scmi_clk CLKID_FCLK_DIV5>, + <&scmi_clk CLKID_FCLK_DIV7>, + <&clkc_pll CLKID_GP0_PLL>, + <&scmi_clk CLKID_GP1_PLL>, + <&clkc_pll CLKID_HIFI_PLL>, + <&scmi_clk CLKID_SYS_CLK>, + <&scmi_clk CLKID_AXI_CLK>, + <&scmi_clk CLKID_SYS_PLL_DIV16>, + <&scmi_clk CLKID_CPU_CLK_DIV16>; + clock-names =3D "xtal", + "oscin", + "fix", + "fdiv2", + "fdiv2p5", + "fdiv3", + "fdiv4", + "fdiv5", + "fdiv7", + "gp0", + "gp1", + "hifi", + "sysclk", + "axiclk", + "sysplldiv16", + "cpudiv16"; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,a4-peripherals-clkc.h b/incl= ude/dt-bindings/clock/amlogic,a4-peripherals-clkc.h new file mode 100644 index 000000000000..b09f4bb4d0d0 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a4-peripherals-clkc.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2025 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu + */ + +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_A4_PERIPHERALS_CLKC_H +#define _DT_BINDINGS_CLOCK_AMLOGIC_A4_PERIPHERALS_CLKC_H + +#define CLKID_RTC_DUALDIV_CLKIN 0 +#define CLKID_RTC_DUALDIV 1 +#define CLKID_RTC_DUALDIV_SEL 2 +#define CLKID_RTC_DUALDIV_CLKOUT 3 +#define CLKID_RTC_CLK 4 +#define CLKID_SYS_RESET_CTRL 5 +#define CLKID_SYS_PWR_CTRL 6 +#define CLKID_SYS_PAD_CTRL 7 +#define CLKID_SYS_CTRL 8 +#define CLKID_SYS_TS_PLL 9 +#define CLKID_SYS_DEV_ARB 10 +#define CLKID_SYS_MAILBOX 11 +#define CLKID_SYS_JTAG_CTRL 12 +#define CLKID_SYS_IR_CTRL 13 +#define CLKID_SYS_MSR_CLK 14 +#define CLKID_SYS_ROM 15 +#define CLKID_SYS_CPU_ARB 16 +#define CLKID_SYS_RSA 17 +#define CLKID_SYS_SARADC 18 +#define CLKID_SYS_STARTUP 19 +#define CLKID_SYS_SECURE 20 +#define CLKID_SYS_SPIFC 21 +#define CLKID_SYS_LED_CTRL 22 +#define CLKID_SYS_ETH_PHY 23 +#define CLKID_SYS_ETH_MAC 24 +#define CLKID_SYS_RAMA 25 +#define CLKID_SYS_RAMB 26 +#define CLKID_SYS_AUDIO_TOP 27 +#define CLKID_SYS_AUDIO_VAD 28 +#define CLKID_SYS_USB 29 +#define CLKID_SYS_SD_EMMC_A 30 +#define CLKID_SYS_SD_EMMC_C 31 +#define CLKID_SYS_PWM_AB 32 +#define CLKID_SYS_PWM_CD 33 +#define CLKID_SYS_PWM_EF 34 +#define CLKID_SYS_PWM_GH 35 +#define CLKID_SYS_SPICC_1 36 +#define CLKID_SYS_SPICC_0 37 +#define CLKID_SYS_UART_A 38 +#define CLKID_SYS_UART_B 39 +#define CLKID_SYS_UART_C 40 +#define CLKID_SYS_UART_D 41 +#define CLKID_SYS_UART_E 42 +#define CLKID_SYS_I2C_M_A 43 +#define CLKID_SYS_I2C_M_B 44 +#define CLKID_SYS_I2C_M_C 45 +#define CLKID_SYS_I2C_M_D 46 +#define CLKID_SYS_RTC 47 +#define CLKID_SYS_VOUT 48 +#define CLKID_SYS_ACODEC 49 +#define CLKID_SYS_USB_CTRL 50 +#define CLKID_AXI_AUDIO_VAD 51 +#define CLKID_AXI_AUDIO_TOP 52 +#define CLKID_AXI_RAMA 53 +#define CLKID_AXI_DEV1_DMC 54 +#define CLKID_AXI_DEV0_DMC 55 +#define CLKID_AXI_DSP_DMC 56 +#define CLKID_12_24M_IN 57 +#define CLKID_12M_24M 58 +#define CLKID_FCLK_25M_DIV 59 +#define CLKID_FCLK_25M 60 +#define CLKID_GEN_SEL 61 +#define CLKID_GEN_DIV 62 +#define CLKID_GEN 63 +#define CLKID_SARADC_SEL 64 +#define CLKID_SARADC_DIV 65 +#define CLKID_SARADC 66 +#define CLKID_PWM_A_SEL 67 +#define CLKID_PWM_A_DIV 68 +#define CLKID_PWM_A 69 +#define CLKID_PWM_B_SEL 70 +#define CLKID_PWM_B_DIV 71 +#define CLKID_PWM_B 72 +#define CLKID_PWM_C_SEL 73 +#define CLKID_PWM_C_DIV 74 +#define CLKID_PWM_C 75 +#define CLKID_PWM_D_SEL 76 +#define CLKID_PWM_D_DIV 77 +#define CLKID_PWM_D 78 +#define CLKID_PWM_E_SEL 79 +#define CLKID_PWM_E_DIV 80 +#define CLKID_PWM_E 81 +#define CLKID_PWM_F_SEL 82 +#define CLKID_PWM_F_DIV 83 +#define CLKID_PWM_F 84 +#define CLKID_PWM_G_SEL 85 +#define CLKID_PWM_G_DIV 86 +#define CLKID_PWM_G 87 +#define CLKID_PWM_H_SEL 88 +#define CLKID_PWM_H_DIV 89 +#define CLKID_PWM_H 90 +#define CLKID_SPICC_0_SEL 91 +#define CLKID_SPICC_0_DIV 92 +#define CLKID_SPICC_0 93 +#define CLKID_SPICC_1_SEL 94 +#define CLKID_SPICC_1_DIV 95 +#define CLKID_SPICC_1 96 +#define CLKID_SD_EMMC_A_SEL 97 +#define CLKID_SD_EMMC_A_DIV 98 +#define CLKID_SD_EMMC_A 99 +#define CLKID_SD_EMMC_C_SEL 100 +#define CLKID_SD_EMMC_C_DIV 101 +#define CLKID_SD_EMMC_C 102 +#define CLKID_TS_DIV 103 +#define CLKID_TS 104 +#define CLKID_ETH_125M_DIV 105 +#define CLKID_ETH_125M 106 +#define CLKID_ETH_RMII_DIV 107 +#define CLKID_ETH_RMII 108 +#define CLKID_VOUT_MCLK_SEL 109 +#define CLKID_VOUT_MCLK_DIV 110 +#define CLKID_VOUT_MCLK 111 +#define CLKID_VOUT_ENC_SEL 112 +#define CLKID_VOUT_ENC_DIV 113 +#define CLKID_VOUT_ENC 114 +#define CLKID_AUDIO_CORE_SEL 115 +#define CLKID_AUDIO_CORE_DIV 116 +#define CLKID_AUDIO_CORE 117 + +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_A4_PERIPHERALS_CLKC_H */ --=20 2.42.0 From nobody Wed Dec 17 14:13:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3D212F5467; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225051; cv=none; b=A7H0isnnWl2lcXX/MqTECnmMosbL/kKYu6vh31vXVEWIS1dI93Ytnz2DDe14ih36gFsseh1hzLqPqrmyEttnB6HzssIURoGysu2bhAa0NpGU0tAmM6DcJPpO4SqbZFkrCZx9psnW+5hnfg8qkesUk6VyWgy/ReH2IIPVXkNOogI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225051; c=relaxed/simple; bh=xSFNma5kv9uRMjcs2Zg6YvItQ9oibLK1g7/ya6UY/2A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PxcfJ3sOzz0mpKg6FWV5WvEVWEoI6jTj/xDHwnkm0q0Wvsp8KlS+NbQAnHy5MfYnxAX9CMuNdQCuhBNe22neK+w6XnHpR63VS6P3BxxOwxVNuEnyBnNFFQTcESzDXPybsvhNa89mPqnf1pq9ZCe7uxyAbbnyzIlQidmYI/wVw8Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kJiebdhS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kJiebdhS" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7786FC19423; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225051; bh=xSFNma5kv9uRMjcs2Zg6YvItQ9oibLK1g7/ya6UY/2A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=kJiebdhS0iQfAhEkjbQEgoG2Sh0gi62VOzBEuVqM4RFGw75EDopbk63HcNcytp0Nh 1P0RXoqRZt6morH+JNGzTUvkOoVyHRTxgyxI61weKOFreti8pXVEVC7NX+2jM461Qb pp3KncumjN9m1V00ZTCqgLm+qy/1G4vdvYiTj3gko4amtBmdSxHVXb5tVgmY8a99e9 HYGNOWF9/OkwYsErwUsScTk88H7O2bce3hbJdte+eXz7oMLgr5ZF7uZbjSmOk/Faf1 CqEXUC09IqNnewtaviL5g+Kb1gHvNNxyF3Qhm37msSGRjDaOpVBFV6TNTHQzrqRWLr 8vuOswk+AbjfQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7111BCAC5B8; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:17 +0800 Subject: [PATCH 04/19] clk: amlogic: Optimize PLL enable timing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-a4_a5_add_clock_driver-v1-4-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=4402; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=PzFaqdiB29ZTMBFFJF+oqAAIU1PhzxewgE9YIWzfRkU=; b=ONDU8yztC1N/PHzG/ebRAKgecCq6KD0moKrXNxd9ZqXIVzWLO8oVq61BriGtki7XdS++VNYOd 7PEyWpTaHlXD6U2Z8E39QXg14Ky38eYdTlXUGLX5YF6VSCPdAbzLYHu X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Amlogic PLL locking procedure shall follow this timing sequence: 1 Assert reset signal: Ensures PLL circuits enter known initial state. 2 Deassert lock-detect signal: Avoid lock signal false triggering. 3 Assert enable signal: Powers up PLL supply. 4 udelay(20): Wait for Bandgap and LDO to power up and stabilize. 5 Enable self-adaptation current module (Optional). 6 Deassert reset signal: Releases PLL to begin normal operation. 7 udelay(20): Wait for PLL loop stabilization. 8 Assert lock-detect signal: lock detection circuit starts to work. 9 Monitor lock status signal: Wait for PLL lock completion. 10 If the PLL fails to lock, it should be disabled, This makes the logic more complete, and also helps save unnecessary power consumption when the PLL is malfunctioning. Signed-off-by: Chuan Liu --- drivers/clk/meson/clk-pll.c | 68 ++++++++++++++++++++++++++---------------= ---- 1 file changed, 40 insertions(+), 28 deletions(-) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 1ea6579a760f..8bddd44d4738 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -353,6 +353,23 @@ static int meson_clk_pcie_pll_enable(struct clk_hw *hw) return -EIO; } =20 +static void meson_clk_pll_disable(struct clk_hw *hw) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct meson_clk_pll_data *pll =3D meson_clk_pll_data(clk); + + /* Put the pll is in reset */ + if (MESON_PARM_APPLICABLE(&pll->rst)) + meson_parm_write(clk->map, &pll->rst, 1); + + /* Disable the pll */ + meson_parm_write(clk->map, &pll->en, 0); + + /* Disable PLL internal self-adaption current module */ + if (MESON_PARM_APPLICABLE(&pll->current_en)) + meson_parm_write(clk->map, &pll->current_en, 0); +} + static int meson_clk_pll_enable(struct clk_hw *hw) { struct clk_regmap *clk =3D to_clk_regmap(hw); @@ -366,53 +383,48 @@ static int meson_clk_pll_enable(struct clk_hw *hw) if (MESON_PARM_APPLICABLE(&pll->rst)) meson_parm_write(clk->map, &pll->rst, 1); =20 + /* Disable the PLL lock-detect module */ + if (MESON_PARM_APPLICABLE(&pll->l_detect)) + meson_parm_write(clk->map, &pll->l_detect, 1); + /* Enable the pll */ meson_parm_write(clk->map, &pll->en, 1); - - /* Take the pll out reset */ - if (MESON_PARM_APPLICABLE(&pll->rst)) - meson_parm_write(clk->map, &pll->rst, 0); + /* Wait for Bandgap and LDO to power up and stabilize */ + udelay(20); =20 /* * Compared with the previous SoCs, self-adaption current module * is newly added for A1, keep the new power-on sequence to enable the * PLL. The sequence is: - * 1. enable the pll, delay for 10us + * 1. enable the pll, ensure a minimum delay of 10=CE=BCs * 2. enable the pll self-adaption current module, delay for 40us * 3. enable the lock detect module */ if (MESON_PARM_APPLICABLE(&pll->current_en)) { - udelay(10); meson_parm_write(clk->map, &pll->current_en, 1); - udelay(40); - } - - if (MESON_PARM_APPLICABLE(&pll->l_detect)) { - meson_parm_write(clk->map, &pll->l_detect, 1); - meson_parm_write(clk->map, &pll->l_detect, 0); + udelay(20); } =20 - if (meson_clk_pll_wait_lock(hw)) - return -EIO; + /* Take the pll out reset */ + if (MESON_PARM_APPLICABLE(&pll->rst)) + meson_parm_write(clk->map, &pll->rst, 0); =20 - return 0; -} + /* Wait for PLL loop stabilization */ + udelay(20); =20 -static void meson_clk_pll_disable(struct clk_hw *hw) -{ - struct clk_regmap *clk =3D to_clk_regmap(hw); - struct meson_clk_pll_data *pll =3D meson_clk_pll_data(clk); + /* Enable the lock-detect module */ + if (MESON_PARM_APPLICABLE(&pll->l_detect)) + meson_parm_write(clk->map, &pll->l_detect, 0); =20 - /* Put the pll is in reset */ - if (MESON_PARM_APPLICABLE(&pll->rst)) - meson_parm_write(clk->map, &pll->rst, 1); + if (meson_clk_pll_wait_lock(hw)) { + /* disable PLL when PLL lock failed. */ + meson_clk_pll_disable(hw); + pr_warn("%s: PLL lock failed!!!\n", clk_hw_get_name(hw)); =20 - /* Disable the pll */ - meson_parm_write(clk->map, &pll->en, 0); + return -EIO; + } =20 - /* Disable PLL internal self-adaption current module */ - if (MESON_PARM_APPLICABLE(&pll->current_en)) - meson_parm_write(clk->map, &pll->current_en, 0); + return 0; } =20 static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, --=20 2.42.0 From nobody Wed Dec 17 14:13:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 362872F6574; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; cv=none; b=mEcA15PysjU5UEWqgCpSmnSDmFH38DHtEHPgu1oAiRFDumQyCxSjRSsMHBfBRGwuH+gx7lJ+M9BwLvlFamQoree0wnY+v3I4ShxyJKUGQzluPxPW5isuxHYuM2wCKyHPHSKfloMMcRkTUS9xnqt0H0kUyLsDCXPp8bc0hkYPBTQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; c=relaxed/simple; bh=Bo1CFOtg4gIIbGHHtViZt9t2cUZjQ5keBMKPre0nFbA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kg8BHXjBReN0lMHWxtqJde721ntA0KHncP3HLRfRmzp0cnKaOj+k5hpuSztqFHXXLlApEBUIWCpoQa5DDP4UR7G5P/PelkmRM9Wvbd3LAr4UugiMH1+IKwiRqUuxqHAoQoKXdU8/hV+QlqhRaPAem1gEckdIu8BylXYWnmNgNOM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GPfn31fg; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GPfn31fg" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8CAB8C19425; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225051; bh=Bo1CFOtg4gIIbGHHtViZt9t2cUZjQ5keBMKPre0nFbA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=GPfn31fgjG1WCcX9ALUQsxP89/Qfck26jzsNY9XnrKfhV/yXKeAws1Kq0O0201Z9v ow5TtEoDEEBUzqsEj+aYjQXG82ZQuj/eL+9xm3SFkHMTyNIEH50U0c+ZYEXEpneXHL xQHXu238GR8JPzZANR0ut1CMTGVmhMC27j5oIUZYZIK2bAgGAw0ymO7fgBf4dfcWB7 9KLroX1CzB8Jh2ETP/ApgqgaP1ax9kwXjggy+SU1uWNHV0QApfbshMFdsBX3fvdwmf m9t4AXxa37ZVXsbcV7yjUj5Lz5SirXrKfbfTFSlRXt6rDPmKaHUnIXyYjGa7Lowe5k 8vK6roUnLCA8Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 801B5CAC5BC; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:18 +0800 Subject: [PATCH 05/19] clk: amlogic: Correct l_detect bit control Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-a4_a5_add_clock_driver-v1-5-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=2616; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=LtshPz5QhFtZiWYcR/aI7iIkvqDd3NT0MWjkTbs07gA=; b=pVc8LO0dn09seJBcSmtce0lp3bWlsFa5f3MvlD1HYbzetWEr7JIaBPn2THXXkqz1OKnWyZ1jX Y9vw3nm/3PHDfiH5MrxfhloJIvhwZ3Nfkx8qYHld3DZY+smlimqbrKU X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu l_detect controls the enable/disable of the PLL lock-detect module. For A1, the l_detect signal is active-low: 0 -> Enable lock-detect module; 1 -> Disable lock-detect module. Signed-off-by: Chuan Liu --- drivers/clk/meson/a1-pll.c | 1 + drivers/clk/meson/clk-pll.c | 16 ++++++++++++---- drivers/clk/meson/clk-pll.h | 2 ++ 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c index 1f82e9c7c14e..bfe559c71402 100644 --- a/drivers/clk/meson/a1-pll.c +++ b/drivers/clk/meson/a1-pll.c @@ -137,6 +137,7 @@ static struct clk_regmap a1_hifi_pll =3D { .range =3D &a1_hifi_pll_range, .init_regs =3D a1_hifi_pll_init_regs, .init_count =3D ARRAY_SIZE(a1_hifi_pll_init_regs), + .flags =3D CLK_MESON_PLL_L_DETECT_N }, .hw.init =3D &(struct clk_init_data){ .name =3D "hifi_pll", diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 8bddd44d4738..c1e4c5710015 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -384,8 +384,12 @@ static int meson_clk_pll_enable(struct clk_hw *hw) meson_parm_write(clk->map, &pll->rst, 1); =20 /* Disable the PLL lock-detect module */ - if (MESON_PARM_APPLICABLE(&pll->l_detect)) - meson_parm_write(clk->map, &pll->l_detect, 1); + if (MESON_PARM_APPLICABLE(&pll->l_detect)) { + if (pll->flags & CLK_MESON_PLL_L_DETECT_N) + meson_parm_write(clk->map, &pll->l_detect, 1); + else + meson_parm_write(clk->map, &pll->l_detect, 0); + } =20 /* Enable the pll */ meson_parm_write(clk->map, &pll->en, 1); @@ -413,8 +417,12 @@ static int meson_clk_pll_enable(struct clk_hw *hw) udelay(20); =20 /* Enable the lock-detect module */ - if (MESON_PARM_APPLICABLE(&pll->l_detect)) - meson_parm_write(clk->map, &pll->l_detect, 0); + if (MESON_PARM_APPLICABLE(&pll->l_detect)) { + if (pll->flags & CLK_MESON_PLL_L_DETECT_N) + meson_parm_write(clk->map, &pll->l_detect, 0); + else + meson_parm_write(clk->map, &pll->l_detect, 1); + } =20 if (meson_clk_pll_wait_lock(hw)) { /* disable PLL when PLL lock failed. */ diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h index 949157fb7bf5..83295a24721f 100644 --- a/drivers/clk/meson/clk-pll.h +++ b/drivers/clk/meson/clk-pll.h @@ -29,6 +29,8 @@ struct pll_mult_range { =20 #define CLK_MESON_PLL_ROUND_CLOSEST BIT(0) #define CLK_MESON_PLL_NOINIT_ENABLED BIT(1) +/* l_detect signal is active-low */ +#define CLK_MESON_PLL_L_DETECT_N BIT(2) =20 struct meson_clk_pll_data { struct parm en; --=20 2.42.0 From nobody Wed Dec 17 14:13:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33B8F2F656F; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; cv=none; b=So7K6LRtRfF/jQw2PVgGFlFq+T/mM0xROonfJmOewGYF0YOWCd6nd+4ikXN3GMc8lZfflQGE19MM1NLW8+CnIB+zCNaVow5DvyHgwpvn169vXWUlapZSYLpk2Ww3yqAy/p4S+xNGBccqpXPnhJRoep5a5TvfrXKQmz4yzuFKDOI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; c=relaxed/simple; bh=YxnyBmHxHXzYw9b8hnimJetb+1Ax5l5URVrr4n8BLuQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sULXMzBBXbJ5BZmgtCruKQ8OStMZYGWWI7koOKuI1P8Cs9yLjyP9F1RpAURzjZZHQa00PJic9NkiWgMdvf1RtJJCVicX2/OmYWOtoLSKNnpUevqSlU3AfDRigP6ts043wU475ZtE7ThttSd6NLmNyuApQlOzJIY0MZJa69AAInA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nbowOD04; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nbowOD04" Received: by smtp.kernel.org (Postfix) with ESMTPS id 98B3FC2BCAF; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225051; bh=YxnyBmHxHXzYw9b8hnimJetb+1Ax5l5URVrr4n8BLuQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=nbowOD043XUfT4f0Yxlyoo5OVZnB40eqlO5t0xPQxBSSD9JI7WyKAUgg3Q8OfWhw5 RL6MIcbXGMn+URG1vzBPntmntV7sXXl6IbzkuhO8LnmJzt9vdTVv6dVgOQmZkcGWz3 HkmGGkBwypfBdybroOOoeFnkeg0fUwYQUi8Or6c2d8xc+Djo3M4H52l+RxDKZKFbcN U9UZ6eKq1HDUc8r3kAD5Th0ozB2gGSCcLNxYFAcVW8U7D4LrTfDFLSJhGwKbChaxDk DdS21jjICCK6FLPJdR56svsHekatDhrJAzw/ycwQEEw7zjiCFCcQhn8r5Yeh3k7QpH wwyPZ8KAlP92g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F50CCCA46F; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:19 +0800 Subject: [PATCH 06/19] clk: amlogic: Fix out-of-range PLL frequency setting Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-a4_a5_add_clock_driver-v1-6-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=799; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=N/UanqAAstFKaIoQ6E9vlI4RDukLeWAnvo1MhrWVBkQ=; b=NIGYgjmhjY3pQ4TkcHp0Hu/MXYaxJFmjLqUACPK6UAcYyXgxSZv9INdR2f7JW4NPfchtH+Zg6 xq0i+9MDrAkDlwweTsVFFpVntkLGXyDpWktoIks9BoSUXNbAlLfgsdA X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu meson_clk_get_pll_range_index incorrectly determines the maximum value of 'm'. Fixes: 8eed1db1adec6 ("clk: meson: pll: update driver for the g12a") Signed-off-by: Chuan Liu --- drivers/clk/meson/clk-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index c1e4c5710015..602c93aba3cc 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -191,7 +191,7 @@ static int meson_clk_get_pll_range_index(unsigned long = rate, *m =3D meson_clk_get_pll_range_m(rate, parent_rate, *n, pll); =20 /* the pre-divider gives a multiplier too big - stop */ - if (*m >=3D (1 << pll->m.width)) + if (*m > pll->range->max) return -EINVAL; =20 return 0; --=20 2.42.0 From nobody Wed Dec 17 14:13:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED08E2F5A1F; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; cv=none; b=Gu/smRYKGfBJ4/Yyx4VoNRfxaVL/h9UIWD6OMPL3NvZ8O25iJfRQ8vjuMbON2xIEx49f/MXwp4lwv2WPdGpjgyA8+J+bBmlQAeQlU0JT0R7LSd6cJu7ZxDVecHNzIH/oLRifmpCugn77RamnIy7LBOf/D4HZ+g3/RK22QM24Bas= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; c=relaxed/simple; bh=/tXAhb7r9S5fNKsT+RVj4pOb6NzJPefkOEiu0n2Zl1w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=B9P75T/9cQur7rBU3wofVIo7kKjTAky1UKfDWb2XxoqLNWld5mld+TRozO7L6ljWWY4Y1ONHnQuvBfE3EVidu0sC+38VdelCREaQIKYmKX0YlHCtY1FCO838jEA4UOhzz+v6XviS4gPViq3nxSHO37azU2vV+dwpQsZS3h1ACbE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PaIvcX+T; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PaIvcX+T" Received: by smtp.kernel.org (Postfix) with ESMTPS id A9BFCC2BCB0; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225051; bh=/tXAhb7r9S5fNKsT+RVj4pOb6NzJPefkOEiu0n2Zl1w=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=PaIvcX+Tug8N/BJ9pXjrLXjlW2VfmnlUPXHI3G1uMtzqkYXOOhG96P1Cq5k+GVyEs hxqUiRHliqdtdhXu7NtbyZVnqEiXuDDX4BhsM86g6eboKGkO4y4M2hnQ9f36ZGbJle OCafp2B/JFOYfbOkdO/aQKQ29mRorgTr8VmemzgTjaphs6UHo+wcEYDKquc9LU/3oV c7nqZplSmCAhdsM+QvytRxJIEJ7Rp8voUoBU8wkFu9u+X25l2jONUYcQcP5A+5/cXA oSjSUZRmCAY7Ude73FJ85ccJENUY7lWrKZ8N/oPMjGmcnHKOtTDNMdwSchdK1aJV9p lmaBvAnbei29g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EBC3CAC5B9; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:20 +0800 Subject: [PATCH 07/19] clk: amlogic: Add A4 PLL clock controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-a4_a5_add_clock_driver-v1-7-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=7766; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=r2T/Rtty/xWtWoEVg0jJRgxPprY4dwBN+xh/xtueO8k=; b=FcB2Wk6gT2QTeY8koVeN6tI+VtN3A39+8fj5YUm4B77UN+jDhyuhYUVpzWVCbR5nfOorYaJxB 4S2rap79zCUAXnugImsaU4Gz0gDUuBNvhUUKbLovHaqfXIaghPKb8mr X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the PLL clock controller driver for the Amlogic A4 SoC family. Signed-off-by: Chuan Liu --- drivers/clk/meson/Kconfig | 13 +++ drivers/clk/meson/Makefile | 1 + drivers/clk/meson/a4-pll.c | 242 +++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 256 insertions(+) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 71481607a6d5..2339abfa2c4e 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -132,6 +132,19 @@ config COMMON_CLK_A1_PERIPHERALS device, A1 SoC Family. Say Y if you want A1 Peripherals clock controller to work. =20 +config COMMON_CLK_A4_PLL + tristate "Amlogic A4 PLL clock controller" + depends on ARM64 + default ARCH_MESON + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_PLL + select COMMON_CLK_MESON_CLKC_UTILS + imply COMMON_CLK_SCMI + help + Support for the PLL clock controller on Amlogic BA40X device, AKA A4. + Say Y if you want the board to work, because PLLs are the parent + of most peripherals. + config COMMON_CLK_C3_PLL tristate "Amlogic C3 PLL clock controller" depends on ARM64 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index c6998e752c68..22312393663f 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_COMMON_CLK_AXG) +=3D axg.o axg-aoclk.o obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) +=3D axg-audio.o obj-$(CONFIG_COMMON_CLK_A1_PLL) +=3D a1-pll.o obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) +=3D a1-peripherals.o +obj-$(CONFIG_COMMON_CLK_A4_PLL) +=3D a4-pll.o obj-$(CONFIG_COMMON_CLK_C3_PLL) +=3D c3-pll.o obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) +=3D c3-peripherals.o obj-$(CONFIG_COMMON_CLK_GXBB) +=3D gxbb.o gxbb-aoclk.o diff --git a/drivers/clk/meson/a4-pll.c b/drivers/clk/meson/a4-pll.c new file mode 100644 index 000000000000..b77d4f610843 --- /dev/null +++ b/drivers/clk/meson/a4-pll.c @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Amlogic A4 PLL Controller Driver + * + * Copyright (c) 2025 Amlogic, inc. + * Author: Chuan Liu + */ + +#include +#include +#include "clk-regmap.h" +#include "clk-pll.h" +#include "meson-clkc-utils.h" +#include + +#define GP0PLL_CTRL0 0x80 +#define GP0PLL_CTRL1 0x84 +#define GP0PLL_CTRL2 0x88 +#define GP0PLL_CTRL3 0x8c +#define HIFIPLL_CTRL0 0x100 +#define HIFIPLL_CTRL1 0x104 +#define HIFIPLL_CTRL2 0x108 +#define HIFIPLL_CTRL3 0x10c + +static const struct reg_sequence a4_gp0_init_regs[] =3D { + { .reg =3D GP0PLL_CTRL1, .def =3D 0x03a00000 }, + { .reg =3D GP0PLL_CTRL2, .def =3D 0x00040000 }, + { .reg =3D GP0PLL_CTRL3, .def =3D 0x090da200 } +}; + +static const struct pll_mult_range a4_gp0_pll_mult_range =3D { + .min =3D 67, + .max =3D 133, +}; + +static struct clk_regmap a4_gp0_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data) { + .en =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 0, + .width =3D 9, + }, + .frac =3D { + .reg_off =3D GP0PLL_CTRL1, + .shift =3D 0, + .width =3D 17, + }, + .n =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 16, + .width =3D 5, + }, + .l =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .l_detect =3D { + .reg_off =3D GP0PLL_CTRL3, + .shift =3D 9, + .width =3D 1, + }, + .range =3D &a4_gp0_pll_mult_range, + .init_regs =3D a4_gp0_init_regs, + .init_count =3D ARRAY_SIZE(a4_gp0_init_regs), + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gp0_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +/* The maximum frequency divider supports is 16, not 128(2^7) */ +static const struct clk_div_table a4_gp0_pll_od_table[] =3D { + { 0, 1 }, + { 1, 2 }, + { 2, 4 }, + { 3, 8 }, + { 4, 16 }, + { /* sentinel */ } +}; + +static struct clk_regmap a4_gp0_pll =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D GP0PLL_CTRL0, + .shift =3D 10, + .width =3D 3, + .table =3D a4_gp0_pll_od_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gp0_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a4_gp0_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence a4_hifi_init_regs[] =3D { + { .reg =3D HIFIPLL_CTRL1, .def =3D 0x03a00000 }, + { .reg =3D HIFIPLL_CTRL2, .def =3D 0x00040000 }, + { .reg =3D HIFIPLL_CTRL3, .def =3D 0x0a0da200 } +}; + +static const struct pll_mult_range a4_hifi_pll_mult_range =3D { + .min =3D 67, + .max =3D 133, +}; + +static struct clk_regmap a4_hifi_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data) { + .en =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .frac =3D { + .reg_off =3D HIFIPLL_CTRL1, + .shift =3D 0, + .width =3D 17, + }, + .n =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 16, + .width =3D 5, + }, + .l =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .l_detect =3D { + .reg_off =3D HIFIPLL_CTRL3, + .shift =3D 9, + .width =3D 1, + }, + .range =3D &a4_hifi_pll_mult_range, + .init_regs =3D a4_hifi_init_regs, + .init_count =3D ARRAY_SIZE(a4_hifi_init_regs), + .frac_max =3D 100000, + .flags =3D CLK_MESON_PLL_ROUND_CLOSEST, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hifi_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +/* The maximum frequency divider supports is 16, not 128(2^7) */ +static const struct clk_div_table a4_hifi_pll_od_table[] =3D { + { 0, 1 }, + { 1, 2 }, + { 2, 4 }, + { 3, 8 }, + { 4, 16 }, + { /* sentinel */ } +}; + +static struct clk_regmap a4_hifi_pll =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D HIFIPLL_CTRL0, + .shift =3D 10, + .width =3D 3, + .table =3D a4_hifi_pll_od_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hifi_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a4_hifi_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_hw *a4_pll_hw_clks[] =3D { + [CLKID_GP0_PLL_DCO] =3D &a4_gp0_pll_dco.hw, + [CLKID_GP0_PLL] =3D &a4_gp0_pll.hw, + [CLKID_HIFI_PLL_DCO] =3D &a4_hifi_pll_dco.hw, + [CLKID_HIFI_PLL] =3D &a4_hifi_pll.hw +}; + +static const struct meson_clkc_data a4_pll_clkc_data =3D { + .hw_clks =3D { + .hws =3D a4_pll_hw_clks, + .num =3D ARRAY_SIZE(a4_pll_hw_clks), + }, +}; + +static const struct of_device_id a4_pll_clkc_match_table[] =3D { + { + .compatible =3D "amlogic,a4-pll-clkc", + .data =3D &a4_pll_clkc_data, + }, + {} +}; +MODULE_DEVICE_TABLE(of, a4_pll_clkc_match_table); + +static struct platform_driver a4_pll_clkc_driver =3D { + .probe =3D meson_clkc_mmio_probe, + .driver =3D { + .name =3D "a4-pll-clkc", + .of_match_table =3D a4_pll_clkc_match_table, + }, +}; +module_platform_driver(a4_pll_clkc_driver); + +MODULE_DESCRIPTION("Amlogic A4 PLL Clock Controller driver"); +MODULE_AUTHOR("Chuan Liu "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("CLK_MESON"); --=20 2.42.0 From nobody Wed Dec 17 14:13:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7A972F5A0B; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; cv=none; b=BC1De03y+EeC+VIW47iBBryt9qykTY5aprENjyNfNfmXNihooy+T4TkSvEO2TKmIW7eaLXHTnz1rkHRPmN/gv6gG67M5qivedZkUcgrRTx4nzR+3NbTrIKYLuXwHz66dNstk9fXBVkqh7vv7oWhn6osJLqfnqig40LxLuMslfl4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; c=relaxed/simple; bh=CMbWctG5OCyukEj1u4JcLuObNtUTraesG8125yDwKvo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TD+eFIXiz4TBf/UAWSArX5pldDEO7sakLjEGyDw6/5zLhdMqAzpl0VuwLLpXbpjvmMBuVFEJX9FYUUCEUoC55o4poNtRyMUiyhTCmOZV3xg5PEOCeXYJjWmEa9q0fsiMUAhEZlGVmEwUq8Br0HqSmRL3R64nluHDD/EpfTcbBu0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qnDq46cw; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qnDq46cw" Received: by smtp.kernel.org (Postfix) with ESMTPS id BB442C116D0; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225051; bh=CMbWctG5OCyukEj1u4JcLuObNtUTraesG8125yDwKvo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=qnDq46cw1QNqoNL8qpR0xdna+/DaLDHgUZGc1+oTaF9ON1ChIe2nVUGL+i0hcUtqE 6tJ2JKPaihU684+DNhFQ7mv3HdPdUdcN9F5EGEnkt/2FlBd4gqhTZsSDSsFpMTjKMf XTkT6CJTeUTtxGG71Ep2Qj7RrvEy92lNwSVxRrdlq5c1jaT/VQ1QWJ53B8DW6+8Wkp IrhUdLr9GXMFlEceSNkVeInpsVNHsIusoHO3w6WGpuvkYS7SMkTkKcQAMiGhYig4yp l91mfkQniwKfQ6MP149FhByIO9lgUhIr7dEMrK4NJ/a/0NNNdTUzbL1jXvB7EnIiXg Z3BwMczX+J4zQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0B4ACAC5B8; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:21 +0800 Subject: [PATCH 08/19] clk: amlogic: Add A4 clock peripherals controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-a4_a5_add_clock_driver-v1-8-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=27245; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=FYsc4v/O5ThjgrrAJUd9t6p1wVfGeTK/ZwkdD2GdKqI=; b=IrS2CArpBDrRgDgzmDYyfPJwi7Ib7xw3hsMVr/pRMRBsqQevWb12coBvCrA/BDbSOqSrXwjTC H/W70hs3EFiAQccYNWUWU/Rahe13ad2zC4z6UEAn/Hd2I+MS4OZkQ+F X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the peripherals clock controller driver for the Amlogic A4 SoC family. Signed-off-by: Chuan Liu --- drivers/clk/meson/Kconfig | 13 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/a4-peripherals.c | 764 +++++++++++++++++++++++++++++++++= ++++ 3 files changed, 778 insertions(+) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 2339abfa2c4e..860625ca6e9b 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -145,6 +145,19 @@ config COMMON_CLK_A4_PLL Say Y if you want the board to work, because PLLs are the parent of most peripherals. =20 +config COMMON_CLK_A4_PERIPHERALS + tristate "Amlogic A4 peripherals clock controller" + depends on ARM64 + default ARCH_MESON + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_DUALDIV + select COMMON_CLK_MESON_CLKC_UTILS + imply COMMON_CLK_SCMI + imply COMMON_CLK_A4_PLL + help + Support for the Peripherals clock controller on Amlogic BA40X device, + AKA A4. Say Y if you want the peripherals clock to work. + config COMMON_CLK_C3_PLL tristate "Amlogic C3 PLL clock controller" depends on ARM64 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 22312393663f..88f6b336a6ca 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) +=3D axg-audio.o obj-$(CONFIG_COMMON_CLK_A1_PLL) +=3D a1-pll.o obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) +=3D a1-peripherals.o obj-$(CONFIG_COMMON_CLK_A4_PLL) +=3D a4-pll.o +obj-$(CONFIG_COMMON_CLK_A4_PERIPHERALS) +=3D a4-peripherals.o obj-$(CONFIG_COMMON_CLK_C3_PLL) +=3D c3-pll.o obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) +=3D c3-peripherals.o obj-$(CONFIG_COMMON_CLK_GXBB) +=3D gxbb.o gxbb-aoclk.o diff --git a/drivers/clk/meson/a4-peripherals.c b/drivers/clk/meson/a4-peri= pherals.c new file mode 100644 index 000000000000..188a61f71653 --- /dev/null +++ b/drivers/clk/meson/a4-peripherals.c @@ -0,0 +1,764 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Amlogic A4 Peripherals Clock Controller Driver + * + * Copyright (c) 2025 Amlogic, inc. + * Author: Chuan Liu + */ + +#include +#include +#include "clk-regmap.h" +#include "clk-dualdiv.h" +#include "meson-clkc-utils.h" +#include + +#define RTC_BY_OSCIN_CTRL0 0x8 +#define RTC_BY_OSCIN_CTRL1 0xc +#define RTC_CTRL 0x10 +#define SYS_CLK_EN0_REG0 0x44 +#define SYS_CLK_EN0_REG1 0x48 +#define CLK12_24_CTRL 0xa8 +#define AXI_CLK_EN0 0xac +#define TS_CLK_CTRL 0x158 +#define ETH_CLK_CTRL 0x164 +#define NAND_CLK_CTRL 0x168 +#define SD_EMMC_CLK_CTRL 0x16c +#define SPICC_CLK_CTRL 0x174 +#define GEN_CLK_CTRL 0x178 +#define SAR_CLK_CTRL0 0x17c +#define PWM_CLK_AB_CTRL 0x180 +#define PWM_CLK_CD_CTRL 0x184 +#define PWM_CLK_EF_CTRL 0x188 +#define PWM_CLK_GH_CTRL 0x18c +#define VOUTENC_CLK_CTRL 0x204 +#define AUDIO_CLK_CTRL 0x208 + +static struct clk_regmap a4_rtc_dualdiv_clkin =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D RTC_BY_OSCIN_CTRL0, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_dualdiv_clkin", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "oscin", + }, + .num_parents =3D 1, + }, +}; + +static const struct meson_clk_dualdiv_param a4_rtc_dualdiv_table[] =3D { + { 733, 732, 8, 11, 1 }, + { /* sentinel */ } +}; + +static struct clk_regmap a4_rtc_dualdiv =3D { + .data =3D &(struct meson_clk_dualdiv_data) { + .n1 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL0, + .shift =3D 0, + .width =3D 12, + }, + .n2 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL0, + .shift =3D 12, + .width =3D 12, + }, + .m1 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL1, + .shift =3D 0, + .width =3D 12, + }, + .m2 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL1, + .shift =3D 12, + .width =3D 12, + }, + .dual =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .table =3D a4_rtc_dualdiv_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_dualdiv", + .ops =3D &meson_clk_dualdiv_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a4_rtc_dualdiv_clkin.hw + }, + .num_parents =3D 1, + }, +}; + +static const struct clk_parent_data a4_rtc_dualdiv_parent_data[] =3D { + { .hw =3D &a4_rtc_dualdiv.hw }, + { .hw =3D &a4_rtc_dualdiv_clkin.hw } +}; + +static struct clk_regmap a4_rtc_dualdiv_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D RTC_BY_OSCIN_CTRL1, + .mask =3D 0x1, + .shift =3D 24, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_dualdiv_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D a4_rtc_dualdiv_parent_data, + .num_parents =3D ARRAY_SIZE(a4_rtc_dualdiv_parent_data), + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a4_rtc_dualdiv_clkout =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D RTC_BY_OSCIN_CTRL0, + .bit_idx =3D 30, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_dualdiv_clkout", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a4_rtc_dualdiv_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data a4_rtc_clk_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .hw =3D &a4_rtc_dualdiv_clkout.hw }, + { .fw_name =3D "pad_osc" } +}; + +static struct clk_regmap a4_rtc_clk =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D RTC_CTRL, + .mask =3D 0x3, + .shift =3D 0, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_clk", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D a4_rtc_clk_parent_data, + .num_parents =3D ARRAY_SIZE(a4_rtc_clk_parent_data), + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +#define A4_PCLK(_name, _reg, _bit, _pdata, _flags) \ +struct clk_regmap a4_##_name =3D { \ + .data =3D &(struct clk_regmap_gate_data) { \ + .offset =3D (_reg), \ + .bit_idx =3D (_bit), \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name, \ + .ops =3D &clk_regmap_gate_ops, \ + .parent_data =3D (_pdata), \ + .num_parents =3D 1, \ + .flags =3D (_flags), \ + }, \ +} + +static const struct clk_parent_data a4_sys_pclk_parents =3D { .fw_name =3D= "sysclk" }; + +#define A4_SYS_PCLK(_name, _reg, _bit, _flags) \ + A4_PCLK(_name, _reg, _bit, &a4_sys_pclk_parents, _flags) + +static A4_SYS_PCLK(sys_reset_ctrl, SYS_CLK_EN0_REG0, 1, 0); +static A4_SYS_PCLK(sys_pwr_ctrl, SYS_CLK_EN0_REG0, 3, 0); +static A4_SYS_PCLK(sys_pad_ctrl, SYS_CLK_EN0_REG0, 4, 0); +static A4_SYS_PCLK(sys_ctrl, SYS_CLK_EN0_REG0, 5, 0); +static A4_SYS_PCLK(sys_ts_pll, SYS_CLK_EN0_REG0, 6, 0); + +/* + * NOTE: sys_dev_arb provides the clock to the SPICC0 and SPICC1 arbiters = that + * access the AXI bus. + */ +static A4_SYS_PCLK(sys_dev_arb, SYS_CLK_EN0_REG0, 7, 0); +static A4_SYS_PCLK(sys_mailbox, SYS_CLK_EN0_REG0, 10, 0); +static A4_SYS_PCLK(sys_jtag_ctrl, SYS_CLK_EN0_REG0, 12, 0); +static A4_SYS_PCLK(sys_ir_ctrl, SYS_CLK_EN0_REG0, 13, 0); +static A4_SYS_PCLK(sys_msr_clk, SYS_CLK_EN0_REG0, 15, 0); +static A4_SYS_PCLK(sys_rom, SYS_CLK_EN0_REG0, 16, 0); +static A4_SYS_PCLK(sys_cpu_apb, SYS_CLK_EN0_REG0, 18, 0); +static A4_SYS_PCLK(sys_rsa, SYS_CLK_EN0_REG0, 19, 0); +static A4_SYS_PCLK(sys_saradc, SYS_CLK_EN0_REG0, 20, 0); +static A4_SYS_PCLK(sys_startup, SYS_CLK_EN0_REG0, 21, 0); +static A4_SYS_PCLK(sys_secure, SYS_CLK_EN0_REG0, 22, 0); +static A4_SYS_PCLK(sys_spifc, SYS_CLK_EN0_REG0, 23, 0); +static A4_SYS_PCLK(sys_led_ctrl, SYS_CLK_EN0_REG0, 24, 0); +static A4_SYS_PCLK(sys_eth_phy, SYS_CLK_EN0_REG0, 25, 0); +static A4_SYS_PCLK(sys_eth_mac, SYS_CLK_EN0_REG0, 26, 0); +static A4_SYS_PCLK(sys_rama, SYS_CLK_EN0_REG0, 28, 0); +static A4_SYS_PCLK(sys_ramb, SYS_CLK_EN0_REG0, 30, 0); +static A4_SYS_PCLK(sys_audio_top, SYS_CLK_EN0_REG1, 0, 0); +static A4_SYS_PCLK(sys_audio_vad, SYS_CLK_EN0_REG1, 1, 0); +static A4_SYS_PCLK(sys_usb, SYS_CLK_EN0_REG1, 2, 0); +static A4_SYS_PCLK(sys_sd_emmc_a, SYS_CLK_EN0_REG1, 3, 0); +static A4_SYS_PCLK(sys_sd_emmc_c, SYS_CLK_EN0_REG1, 4, 0); +static A4_SYS_PCLK(sys_pwm_ab, SYS_CLK_EN0_REG1, 5, 0); +static A4_SYS_PCLK(sys_pwm_cd, SYS_CLK_EN0_REG1, 6, 0); +static A4_SYS_PCLK(sys_pwm_ef, SYS_CLK_EN0_REG1, 7, 0); +static A4_SYS_PCLK(sys_pwm_gh, SYS_CLK_EN0_REG1, 8, 0); +static A4_SYS_PCLK(sys_spicc_1, SYS_CLK_EN0_REG1, 9, 0); +static A4_SYS_PCLK(sys_spicc_0, SYS_CLK_EN0_REG1, 10, 0); +static A4_SYS_PCLK(sys_uart_a, SYS_CLK_EN0_REG1, 11, 0); +static A4_SYS_PCLK(sys_uart_b, SYS_CLK_EN0_REG1, 12, 0); +static A4_SYS_PCLK(sys_uart_c, SYS_CLK_EN0_REG1, 13, 0); +static A4_SYS_PCLK(sys_uart_d, SYS_CLK_EN0_REG1, 14, 0); +static A4_SYS_PCLK(sys_uart_e, SYS_CLK_EN0_REG1, 15, 0); +static A4_SYS_PCLK(sys_i2c_m_a, SYS_CLK_EN0_REG1, 16, 0); +static A4_SYS_PCLK(sys_i2c_m_b, SYS_CLK_EN0_REG1, 17, 0); +static A4_SYS_PCLK(sys_i2c_m_c, SYS_CLK_EN0_REG1, 18, 0); +static A4_SYS_PCLK(sys_i2c_m_d, SYS_CLK_EN0_REG1, 19, 0); +static A4_SYS_PCLK(sys_rtc, SYS_CLK_EN0_REG1, 21, 0); +static A4_SYS_PCLK(sys_vout, SYS_CLK_EN0_REG1, 22, 0); +static A4_SYS_PCLK(sys_usb_ctrl, SYS_CLK_EN0_REG1, 26, 0); +static A4_SYS_PCLK(sys_acodec, SYS_CLK_EN0_REG1, 27, 0); + +static const struct clk_parent_data a4_axi_clk_parents =3D { .fw_name =3D = "axiclk" }; + +#define A4_AXI_CLK(_name, _reg, _bit, _flags) \ + A4_PCLK(_name, _reg, _bit, &a4_axi_clk_parents, _flags) + +static A4_AXI_CLK(axi_audio_vad, AXI_CLK_EN0, 0, 0); +static A4_AXI_CLK(axi_audio_top, AXI_CLK_EN0, 1, 0); +static A4_AXI_CLK(axi_rama, AXI_CLK_EN0, 6, 0); + +/* + * NOTE: axi_dev1_dmc provides the clock for the peripherals(EMMC, SDIO, + * sec_top, USB, Audio) to access the AXI bus of the DDR. + */ +static A4_AXI_CLK(axi_dev1_dmc, AXI_CLK_EN0, 13, 0); + +/* + * NOTE: axi_dev0_dmc provides the clock for the peripherals(ETH and SPICC) + * to access the AXI bus of the DDR. + */ +static A4_AXI_CLK(axi_dev0_dmc, AXI_CLK_EN0, 14, 0); +static A4_AXI_CLK(axi_dsp_dmc, AXI_CLK_EN0, 15, 0); + +static struct clk_regmap a4_clk_12_24m_in =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLK12_24_CTRL, + .bit_idx =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "clk_12_24m_in", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a4_clk_12_24m =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLK12_24_CTRL, + .shift =3D 10, + .width =3D 1, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "clk_12_24m", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a4_clk_12_24m_in.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a4_fclk_25m_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLK12_24_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_25m_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fix", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a4_fclk_25m =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLK12_24_CTRL, + .bit_idx =3D 12, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_25m", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a4_fclk_25m_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* + * Channel 3(ddr_dpll_pt_clk) is manged by the DDR module; channel 12(cts_= msr_clk) + * is manged by clock measures module. Their hardware are out of clock tre= e. + * Channel 4 5 8 9 10 11 13 14 15 16 18 are not connected. + */ +static u32 a4_gen_parent_table[] =3D { 0, 1, 2, 6, 7, 17, 19, 20, 21, 22, = 23, 24}; + +static const struct clk_parent_data gen_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .hw =3D &a4_rtc_clk.hw }, + { .fw_name =3D "sysplldiv16" }, + { .fw_name =3D "gp1" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "cpudiv16" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "fdiv7" } +}; + +static struct clk_regmap a4_gen_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D GEN_CLK_CTRL, + .mask =3D 0x1f, + .shift =3D 12, + .table =3D a4_gen_parent_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gen_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D gen_parent_data, + .num_parents =3D ARRAY_SIZE(gen_parent_data), + }, +}; + +static struct clk_regmap a4_gen_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D GEN_CLK_CTRL, + .shift =3D 0, + .width =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gen_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a4_gen_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a4_gen =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D GEN_CLK_CTRL, + .bit_idx =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gen", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a4_gen_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +#define A4_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \ + MESON_COMP_SEL(a4_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0) + +#define A4_COMP_DIV(_name, _reg, _shift, _width) \ + MESON_COMP_DIV(a4_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT) + +#define A4_COMP_GATE(_name, _reg, _bit) \ + MESON_COMP_GATE(a4_, _name, _reg, _bit, CLK_SET_RATE_PARENT) + +static const struct clk_parent_data a4_saradc_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "sysclk" } +}; + +static A4_COMP_SEL(saradc, SAR_CLK_CTRL0, 9, 0x3, a4_saradc_parent_data); +static A4_COMP_DIV(saradc, SAR_CLK_CTRL0, 0, 8); +static A4_COMP_GATE(saradc, SAR_CLK_CTRL0, 8); + +static const struct clk_parent_data a4_pwm_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .hw =3D &a4_rtc_clk.hw }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv3" } +}; + +static A4_COMP_SEL(pwm_a, PWM_CLK_AB_CTRL, 9, 0x3, a4_pwm_parent_data); +static A4_COMP_DIV(pwm_a, PWM_CLK_AB_CTRL, 0, 8); +static A4_COMP_GATE(pwm_a, PWM_CLK_AB_CTRL, 8); + +static A4_COMP_SEL(pwm_b, PWM_CLK_AB_CTRL, 25, 0x3, a4_pwm_parent_data); +static A4_COMP_DIV(pwm_b, PWM_CLK_AB_CTRL, 16, 8); +static A4_COMP_GATE(pwm_b, PWM_CLK_AB_CTRL, 24); + +static A4_COMP_SEL(pwm_c, PWM_CLK_CD_CTRL, 9, 0x3, a4_pwm_parent_data); +static A4_COMP_DIV(pwm_c, PWM_CLK_CD_CTRL, 0, 8); +static A4_COMP_GATE(pwm_c, PWM_CLK_CD_CTRL, 8); + +static A4_COMP_SEL(pwm_d, PWM_CLK_CD_CTRL, 25, 0x3, a4_pwm_parent_data); +static A4_COMP_DIV(pwm_d, PWM_CLK_CD_CTRL, 16, 8); +static A4_COMP_GATE(pwm_d, PWM_CLK_CD_CTRL, 24); + +static A4_COMP_SEL(pwm_e, PWM_CLK_EF_CTRL, 9, 0x3, a4_pwm_parent_data); +static A4_COMP_DIV(pwm_e, PWM_CLK_EF_CTRL, 0, 8); +static A4_COMP_GATE(pwm_e, PWM_CLK_EF_CTRL, 8); + +static A4_COMP_SEL(pwm_f, PWM_CLK_EF_CTRL, 25, 0x3, a4_pwm_parent_data); +static A4_COMP_DIV(pwm_f, PWM_CLK_EF_CTRL, 16, 8); +static A4_COMP_GATE(pwm_f, PWM_CLK_EF_CTRL, 24); + +static A4_COMP_SEL(pwm_g, PWM_CLK_GH_CTRL, 9, 0x3, a4_pwm_parent_data); +static A4_COMP_DIV(pwm_g, PWM_CLK_GH_CTRL, 0, 8); +static A4_COMP_GATE(pwm_g, PWM_CLK_GH_CTRL, 8); + +static A4_COMP_SEL(pwm_h, PWM_CLK_GH_CTRL, 25, 0x3, a4_pwm_parent_data); +static A4_COMP_DIV(pwm_h, PWM_CLK_GH_CTRL, 16, 8); +static A4_COMP_GATE(pwm_h, PWM_CLK_GH_CTRL, 24); + +static const struct clk_parent_data a4_spicc_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "sysclk" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "fdiv7" }, + { .fw_name =3D "gp1" } +}; + +static A4_COMP_SEL(spicc_0, SPICC_CLK_CTRL, 7, 0x7, a4_spicc_parent_data); +static A4_COMP_DIV(spicc_0, SPICC_CLK_CTRL, 0, 6); +static A4_COMP_GATE(spicc_0, SPICC_CLK_CTRL, 6); + +static A4_COMP_SEL(spicc_1, SPICC_CLK_CTRL, 23, 0x7, a4_spicc_parent_data); +static A4_COMP_DIV(spicc_1, SPICC_CLK_CTRL, 16, 6); +static A4_COMP_GATE(spicc_1, SPICC_CLK_CTRL, 22); + +#define A4_COMP_SEL_WITH_TAB(_name, _reg, _shift, _mask, _pdata, _table) \ + MESON_COMP_SEL(a4_, _name, _reg, _shift, _mask, _pdata, _table, 0, 0) + +/* Channel 5 6 are not connected. */ +static u32 a4_sd_emmc_parent_table[] =3D { 0, 1, 2, 3, 4, 7}; + +static const struct clk_parent_data a4_sd_emmc_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "gp0" } +}; + +static A4_COMP_SEL_WITH_TAB(sd_emmc_a, SD_EMMC_CLK_CTRL, 9, 0x7, + a4_sd_emmc_parent_data, a4_sd_emmc_parent_table); +static A4_COMP_DIV(sd_emmc_a, SD_EMMC_CLK_CTRL, 0, 7); +static A4_COMP_GATE(sd_emmc_a, SD_EMMC_CLK_CTRL, 7); + +static A4_COMP_SEL_WITH_TAB(sd_emmc_c, NAND_CLK_CTRL, 9, 0x7, + a4_sd_emmc_parent_data, a4_sd_emmc_parent_table); +static A4_COMP_DIV(sd_emmc_c, NAND_CLK_CTRL, 0, 7); +static A4_COMP_GATE(sd_emmc_c, NAND_CLK_CTRL, 7); + +static struct clk_regmap a4_ts_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D TS_CLK_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "ts_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "oscin", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a4_ts =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D TS_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "ts", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a4_ts_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor a4_eth_125m_div =3D { + .mult =3D 1, + .div =3D 8, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_125m_div", + .ops =3D &clk_fixed_factor_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fdiv2", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a4_eth_125m =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ETH_CLK_CTRL, + .bit_idx =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_125m", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a4_eth_125m_div.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a4_eth_rmii_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ETH_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_rmii_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fdiv2", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a4_eth_rmii =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ETH_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_rmii", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a4_eth_rmii_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data a4_vout_mclk_parent_data[] =3D { + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "gp0" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "gp1" }, + { .fw_name =3D "fdiv7" } +}; + +static A4_COMP_SEL(vout_mclk, VOUTENC_CLK_CTRL, 9, 0x7, + a4_vout_mclk_parent_data); +static A4_COMP_DIV(vout_mclk, VOUTENC_CLK_CTRL, 0, 7); +static A4_COMP_GATE(vout_mclk, VOUTENC_CLK_CTRL, 8); + +static const struct clk_parent_data a4_vout_enc_parent_data[] =3D { + { .fw_name =3D "gp1" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "gp0" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv7" } +}; + +static A4_COMP_SEL(vout_enc, VOUTENC_CLK_CTRL, 25, 0x7, + a4_vout_enc_parent_data); +static A4_COMP_DIV(vout_enc, VOUTENC_CLK_CTRL, 16, 7); +static A4_COMP_GATE(vout_enc, VOUTENC_CLK_CTRL, 24); + +static const struct clk_parent_data a4_audio_core_parent_data[] =3D { + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "gp1" } +}; + +static A4_COMP_SEL(audio_core, AUDIO_CLK_CTRL, 9, 0x3, + a4_audio_core_parent_data); +static A4_COMP_DIV(audio_core, AUDIO_CLK_CTRL, 0, 8); +static A4_COMP_GATE(audio_core, AUDIO_CLK_CTRL, 8); + +static struct clk_hw *a4_peripherals_hw_clks[] =3D { + [CLKID_RTC_DUALDIV_CLKIN] =3D &a4_rtc_dualdiv_clkin.hw, + [CLKID_RTC_DUALDIV] =3D &a4_rtc_dualdiv.hw, + [CLKID_RTC_DUALDIV_SEL] =3D &a4_rtc_dualdiv_sel.hw, + [CLKID_RTC_DUALDIV_CLKOUT] =3D &a4_rtc_dualdiv_clkout.hw, + [CLKID_RTC_CLK] =3D &a4_rtc_clk.hw, + [CLKID_SYS_RESET_CTRL] =3D &a4_sys_reset_ctrl.hw, + [CLKID_SYS_PWR_CTRL] =3D &a4_sys_pwr_ctrl.hw, + [CLKID_SYS_PAD_CTRL] =3D &a4_sys_pad_ctrl.hw, + [CLKID_SYS_CTRL] =3D &a4_sys_ctrl.hw, + [CLKID_SYS_TS_PLL] =3D &a4_sys_ts_pll.hw, + [CLKID_SYS_DEV_ARB] =3D &a4_sys_dev_arb.hw, + [CLKID_SYS_MAILBOX] =3D &a4_sys_mailbox.hw, + [CLKID_SYS_JTAG_CTRL] =3D &a4_sys_jtag_ctrl.hw, + [CLKID_SYS_IR_CTRL] =3D &a4_sys_ir_ctrl.hw, + [CLKID_SYS_MSR_CLK] =3D &a4_sys_msr_clk.hw, + [CLKID_SYS_ROM] =3D &a4_sys_rom.hw, + [CLKID_SYS_CPU_ARB] =3D &a4_sys_cpu_apb.hw, + [CLKID_SYS_RSA] =3D &a4_sys_rsa.hw, + [CLKID_SYS_SARADC] =3D &a4_sys_saradc.hw, + [CLKID_SYS_STARTUP] =3D &a4_sys_startup.hw, + [CLKID_SYS_SECURE] =3D &a4_sys_secure.hw, + [CLKID_SYS_SPIFC] =3D &a4_sys_spifc.hw, + [CLKID_SYS_LED_CTRL] =3D &a4_sys_led_ctrl.hw, + [CLKID_SYS_ETH_PHY] =3D &a4_sys_eth_phy.hw, + [CLKID_SYS_ETH_MAC] =3D &a4_sys_eth_mac.hw, + [CLKID_SYS_RAMA] =3D &a4_sys_rama.hw, + [CLKID_SYS_RAMB] =3D &a4_sys_ramb.hw, + [CLKID_SYS_AUDIO_TOP] =3D &a4_sys_audio_top.hw, + [CLKID_SYS_AUDIO_VAD] =3D &a4_sys_audio_vad.hw, + [CLKID_SYS_USB] =3D &a4_sys_usb.hw, + [CLKID_SYS_SD_EMMC_A] =3D &a4_sys_sd_emmc_a.hw, + [CLKID_SYS_SD_EMMC_C] =3D &a4_sys_sd_emmc_c.hw, + [CLKID_SYS_PWM_AB] =3D &a4_sys_pwm_ab.hw, + [CLKID_SYS_PWM_CD] =3D &a4_sys_pwm_cd.hw, + [CLKID_SYS_PWM_EF] =3D &a4_sys_pwm_ef.hw, + [CLKID_SYS_PWM_GH] =3D &a4_sys_pwm_gh.hw, + [CLKID_SYS_SPICC_1] =3D &a4_sys_spicc_1.hw, + [CLKID_SYS_SPICC_0] =3D &a4_sys_spicc_0.hw, + [CLKID_SYS_UART_A] =3D &a4_sys_uart_a.hw, + [CLKID_SYS_UART_B] =3D &a4_sys_uart_b.hw, + [CLKID_SYS_UART_C] =3D &a4_sys_uart_c.hw, + [CLKID_SYS_UART_D] =3D &a4_sys_uart_d.hw, + [CLKID_SYS_UART_E] =3D &a4_sys_uart_e.hw, + [CLKID_SYS_I2C_M_A] =3D &a4_sys_i2c_m_a.hw, + [CLKID_SYS_I2C_M_B] =3D &a4_sys_i2c_m_b.hw, + [CLKID_SYS_I2C_M_C] =3D &a4_sys_i2c_m_c.hw, + [CLKID_SYS_I2C_M_D] =3D &a4_sys_i2c_m_d.hw, + [CLKID_SYS_RTC] =3D &a4_sys_rtc.hw, + [CLKID_SYS_VOUT] =3D &a4_sys_vout.hw, + [CLKID_SYS_USB_CTRL] =3D &a4_sys_usb_ctrl.hw, + [CLKID_SYS_ACODEC] =3D &a4_sys_acodec.hw, + [CLKID_AXI_AUDIO_VAD] =3D &a4_axi_audio_vad.hw, + [CLKID_AXI_AUDIO_TOP] =3D &a4_axi_audio_top.hw, + [CLKID_AXI_RAMA] =3D &a4_axi_rama.hw, + [CLKID_AXI_DEV1_DMC] =3D &a4_axi_dev1_dmc.hw, + [CLKID_AXI_DEV0_DMC] =3D &a4_axi_dev0_dmc.hw, + [CLKID_AXI_DSP_DMC] =3D &a4_axi_dsp_dmc.hw, + [CLKID_12_24M_IN] =3D &a4_clk_12_24m_in.hw, + [CLKID_12M_24M] =3D &a4_clk_12_24m.hw, + [CLKID_FCLK_25M_DIV] =3D &a4_fclk_25m_div.hw, + [CLKID_FCLK_25M] =3D &a4_fclk_25m.hw, + [CLKID_GEN_SEL] =3D &a4_gen_sel.hw, + [CLKID_GEN_DIV] =3D &a4_gen_div.hw, + [CLKID_GEN] =3D &a4_gen.hw, + [CLKID_SARADC_SEL] =3D &a4_saradc_sel.hw, + [CLKID_SARADC_DIV] =3D &a4_saradc_div.hw, + [CLKID_SARADC] =3D &a4_saradc.hw, + [CLKID_PWM_A_SEL] =3D &a4_pwm_a_sel.hw, + [CLKID_PWM_A_DIV] =3D &a4_pwm_a_div.hw, + [CLKID_PWM_A] =3D &a4_pwm_a.hw, + [CLKID_PWM_B_SEL] =3D &a4_pwm_b_sel.hw, + [CLKID_PWM_B_DIV] =3D &a4_pwm_b_div.hw, + [CLKID_PWM_B] =3D &a4_pwm_b.hw, + [CLKID_PWM_C_SEL] =3D &a4_pwm_c_sel.hw, + [CLKID_PWM_C_DIV] =3D &a4_pwm_c_div.hw, + [CLKID_PWM_C] =3D &a4_pwm_c.hw, + [CLKID_PWM_D_SEL] =3D &a4_pwm_d_sel.hw, + [CLKID_PWM_D_DIV] =3D &a4_pwm_d_div.hw, + [CLKID_PWM_D] =3D &a4_pwm_d.hw, + [CLKID_PWM_E_SEL] =3D &a4_pwm_e_sel.hw, + [CLKID_PWM_E_DIV] =3D &a4_pwm_e_div.hw, + [CLKID_PWM_E] =3D &a4_pwm_e.hw, + [CLKID_PWM_F_SEL] =3D &a4_pwm_f_sel.hw, + [CLKID_PWM_F_DIV] =3D &a4_pwm_f_div.hw, + [CLKID_PWM_F] =3D &a4_pwm_f.hw, + [CLKID_PWM_G_SEL] =3D &a4_pwm_g_sel.hw, + [CLKID_PWM_G_DIV] =3D &a4_pwm_g_div.hw, + [CLKID_PWM_G] =3D &a4_pwm_g.hw, + [CLKID_PWM_H_SEL] =3D &a4_pwm_h_sel.hw, + [CLKID_PWM_H_DIV] =3D &a4_pwm_h_div.hw, + [CLKID_PWM_H] =3D &a4_pwm_h.hw, + [CLKID_SPICC_0_SEL] =3D &a4_spicc_0_sel.hw, + [CLKID_SPICC_0_DIV] =3D &a4_spicc_0_div.hw, + [CLKID_SPICC_0] =3D &a4_spicc_0.hw, + [CLKID_SPICC_1_SEL] =3D &a4_spicc_1_sel.hw, + [CLKID_SPICC_1_DIV] =3D &a4_spicc_1_div.hw, + [CLKID_SPICC_1] =3D &a4_spicc_1.hw, + [CLKID_SD_EMMC_A_SEL] =3D &a4_sd_emmc_a_sel.hw, + [CLKID_SD_EMMC_A_DIV] =3D &a4_sd_emmc_a_div.hw, + [CLKID_SD_EMMC_A] =3D &a4_sd_emmc_a.hw, + [CLKID_SD_EMMC_C_SEL] =3D &a4_sd_emmc_c_sel.hw, + [CLKID_SD_EMMC_C_DIV] =3D &a4_sd_emmc_c_div.hw, + [CLKID_SD_EMMC_C] =3D &a4_sd_emmc_c.hw, + [CLKID_TS_DIV] =3D &a4_ts_div.hw, + [CLKID_TS] =3D &a4_ts.hw, + [CLKID_ETH_125M_DIV] =3D &a4_eth_125m_div.hw, + [CLKID_ETH_125M] =3D &a4_eth_125m.hw, + [CLKID_ETH_RMII_DIV] =3D &a4_eth_rmii_div.hw, + [CLKID_ETH_RMII] =3D &a4_eth_rmii.hw, + [CLKID_VOUT_MCLK_SEL] =3D &a4_vout_mclk_sel.hw, + [CLKID_VOUT_MCLK_DIV] =3D &a4_vout_mclk_div.hw, + [CLKID_VOUT_MCLK] =3D &a4_vout_mclk.hw, + [CLKID_VOUT_ENC_SEL] =3D &a4_vout_enc_sel.hw, + [CLKID_VOUT_ENC_DIV] =3D &a4_vout_enc_div.hw, + [CLKID_VOUT_ENC] =3D &a4_vout_enc.hw, + [CLKID_AUDIO_CORE_SEL] =3D &a4_audio_core_sel.hw, + [CLKID_AUDIO_CORE_DIV] =3D &a4_audio_core_div.hw, + [CLKID_AUDIO_CORE] =3D &a4_audio_core.hw, +}; + +static const struct meson_clkc_data a4_peripherals_clkc_data =3D { + .hw_clks =3D { + .hws =3D a4_peripherals_hw_clks, + .num =3D ARRAY_SIZE(a4_peripherals_hw_clks), + }, +}; + +static const struct of_device_id a4_peripherals_clkc_match_table[] =3D { + { + .compatible =3D "amlogic,a4-peripherals-clkc", + .data =3D &a4_peripherals_clkc_data, + }, + {} +}; +MODULE_DEVICE_TABLE(of, a4_peripherals_clkc_match_table); + +static struct platform_driver a4_peripherals_clkc_driver =3D { + .probe =3D meson_clkc_mmio_probe, + .driver =3D { + .name =3D "a4-peripherals-clkc", + .of_match_table =3D a4_peripherals_clkc_match_table, + }, +}; +module_platform_driver(a4_peripherals_clkc_driver); + +MODULE_DESCRIPTION("Amlogic A4 Peripherals Clock Controller driver"); +MODULE_AUTHOR("Chuan Liu "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("CLK_MESON"); --=20 2.42.0 From nobody Wed Dec 17 14:13:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 426692F6599; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; cv=none; b=ALdCNcEl2C7hHNtARWm0pM/LlcJG4iXYcDli/MJysEOEL0+/j7UcBLFvMHSL+HwEed3+PRMjskGITW4U22R31gIqslver8seWFYPKwlkXeTUDEJmAh7wL62Bdz6a0TrzlYS3SR3KR31VqPpJ/n8a/1GymGs/pTAArTdwtuyWrt4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; c=relaxed/simple; bh=m3tcUPTeAy9N3b8of7vcp0PLY10EBp4gFZGLnaPlv6M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PDxo1XN9YTPj1pDEl7sUZTZrqxlLnm3lS8G4oReixqMIu5hqgpJagrIt1rUZHg+y1It3iDYK3woZS8zKrgVvl+TZpsbuO1RDGbYEdK9nBoNw9iuu574locR8k1u9QGphTnyUAhuFLfoBjBknCHs7XVjb3O4oIjYboBXjzZzeJ78= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OPEjn6X1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OPEjn6X1" Received: by smtp.kernel.org (Postfix) with ESMTPS id D3BA9C116C6; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225051; bh=m3tcUPTeAy9N3b8of7vcp0PLY10EBp4gFZGLnaPlv6M=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=OPEjn6X1XzS8pl7W7CUbHiZrYdFOCC4R6XhFwkqMewH7hocoFtKiH1NZSQqv6NFdO tt/Ixu07a+VxwGCZgRh7aDxrYjZT5iHbxRK4mP40EN1lEru7Hm99LhlniHBMwB/J5I ehEOxkXCJHGE4jBGjXiHiFxUJ8VWi1vqcnAc9hoX4C5JifJNZZtX3F1O3kWmeSC966 lBhKnxm/eA0QgIiy/QtdLJucUT7WekNPfRSeEdJ5CdL6Fg+ZLxwT2qL4mqEfKuzrxC FAUyGaOIog3Q6fWWmVnqg3RWWt6IkyuaSBEc6sgmPru9L0huhJMq+um6DbKoQeLYXF 1iSuKkyW2PwNg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C74A6CCA470; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:22 +0800 Subject: [PATCH 09/19] arm64: dts: amlogic: A4: Add scmi-clk node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-a4_a5_add_clock_driver-v1-9-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=1181; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=+Iyb8ucZxc+f5S3pcp3snpI9+yN2dfYAfr8oIOUIHcQ=; b=lcBDqboM/iymoRmBzRwcVori330OjmwhgepC7924uxxFr8NPhQ3vWlz/SUAhF46VD/1UJca2J X4tLUGHjoR8B5T7MHj0vHgNS+dSMKktQ8J6H0QpvswRFRb53ARknA05 X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add scmi-clk device node information for the Amlogic A4 SoC family. Signed-off-by: Chuan Liu --- arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 28 +++++++++++++++++++++++++= +++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-a4.dtsi index 563bc2e662fa..75a87f093d8d 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi @@ -49,6 +49,34 @@ pwrc: power-controller { #power-domain-cells =3D <1>; }; }; + + sram0: sram@f7033000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0xf7033000 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x0 0xf7033000 0x100>; + + scmi_buf0: scmi-sram-section@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x100>; + }; + }; + + firmware { + scmi { + compatible =3D "arm,scmi-smc"; + arm,smc-id =3D <0x820000C1>; + shmem =3D <&scmi_buf0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_clk: protocol@14 { + reg =3D <0x14>; + #clock-cells =3D <1>; + }; + }; + }; }; =20 &apb { --=20 2.42.0 From nobody Wed Dec 17 14:13:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4DC4B2F39DC; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; cv=none; b=W4hYBv3ZoRul4DSxZoZMKIA+04Ktsf6v7ChWYo94Fy7/mZRwf72Ukw14ueB0HojrG+iO84H/GFIcvB4H0CMMsrvQrFfI1HzURIrumUEsEIBySrBAq65YJBi/i+ZaRC5pKouDQRiIh/vpd540+iXUAiMcikisrXUyNlYv3k/Y/Yk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; c=relaxed/simple; bh=IcxSHLYl5CZjSo//DJmvH58mP+K43m312XKis/pZlLY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=U0T5HMdFIlgwUYiWB9xxBwnpH7o+JYkHxbwLevCTWQvG8m4Yd0OX3jURAzny3Za9QRRGVqmdtlFs43UU/ZDpMoYrRKHIoR/RLO6rYnwk5gHsolxZPKqaIR/1Oot+YqF0EFjFiY0XAq+QNaSOrn+27Ifxfl0Z+cFg2yrBDD6iZ8g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JooDNA4E; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JooDNA4E" Received: by smtp.kernel.org (Postfix) with ESMTPS id E1369C4CEF0; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225051; bh=IcxSHLYl5CZjSo//DJmvH58mP+K43m312XKis/pZlLY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=JooDNA4EJDKqRyRYYW/VZUuBjy/yvR/FfKQ/9jUaj8GkQDMbdrY/h8hFc/zffWRYY 5QUBx11BAkcZSflWwoDL0e2uLMZ1AnmejwPNgEHEV20HvBg1uYHBiPssGwjQSJBNzv 5eemiK/sDWr+oRc6I7AuPODsIA+Ha1ICh4AUC7lzGUDqaPHktGwR9L6y2Vs3f7FmBz 7KozslKw+mWqF6jiNaloHRR6pNmi6lmIrzii7rBGGLb01VsgiofTv0OraFrGGIXKGG /j8/aCZPKPpMJYZVo8bPFJ+zBzDL6luHqOiYhT8wRu5y7n9UOjjyPkVLr0URkWGrmh P08DWXXhCsg8A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9BF0CAC5B9; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:23 +0800 Subject: [PATCH 10/19] arm64: dts: amlogic: A4: Add PLL controller node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-a4_a5_add_clock_driver-v1-10-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=1225; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=oAaJfXCorPN/I+5LCtKFDD1NM9mVnKs2qOf9ZPCvDw8=; b=d6myvlj/U/L13Tj+S+Ji4Dk0XtVUxazgUUq9FsVE1ThmjBA/nzBhUa5xmY5macDs7lO7hGqSI M9QAVPVu/svDybUns5YQEHYuQU2bWzRntvXYsqFUQFx2sqtfKKQZrZT X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the PLL controller node for A4 SoC family. Signed-off-by: Chuan Liu --- arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-a4.dtsi index 75a87f093d8d..aca81e658654 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi @@ -7,6 +7,9 @@ #include "amlogic-a4-reset.h" #include #include +#include +#include + / { cpus { #address-cells =3D <2>; @@ -198,6 +201,16 @@ gpio_intc: interrupt-controller@4080 { <10 11 12 13 14 15 16 17 18 19 20 21>; }; =20 + clkc_pll: clock-controller@8000 { + compatible =3D "amlogic,a4-pll-clkc"; + reg =3D <0x0 0x8000 0x0 0x1a4>; + #clock-cells =3D <1>; + clocks =3D <&xtal>, + <&scmi_clk CLKID_FIXED_PLL>; + clock-names =3D "xtal", + "fix"; + }; + ao_pinctrl: pinctrl@8e700 { compatible =3D "amlogic,pinctrl-a4"; #address-cells =3D <2>; --=20 2.42.0 From nobody Wed Dec 17 14:13:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 674802F7462; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; cv=none; b=ReITe6uiwIggL2wR3/h6S9WcX7RI3fTKon+z/2oDFsVwD1dR8m4ieanLCOnLSD+v1qeke0JCrI1lAwuTJJAvoIi36pMoc47vNmZQFS6/+RiwbZwp256IxiXM2UIz1rhhp5AwRkNxfFex0T7NmuwT33+u1AsIOuHYho6vJrxp1lM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; c=relaxed/simple; bh=pJfB4TXNmkLx5PsgtIGHnwAF+cA8RL+QoqrxgmDx/EI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZQfq2l86fgTn2/WAgaw3V4+yz5aLijD+XrUA6osI6QlNYJq6VEfxlgWU+NGIFIIMtNgl+T3ABrGT0qfiwh6o/ULCEE4U+Vob3tR5gWcYJNl+gA2cDCgIo/VBuQBNrGLG2vetoGxgY9syOddM09gfQvkVD17tYNYPezfi2jGv5fo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=a2r9NKlh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="a2r9NKlh" Received: by smtp.kernel.org (Postfix) with ESMTPS id F29BEC113D0; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225052; bh=pJfB4TXNmkLx5PsgtIGHnwAF+cA8RL+QoqrxgmDx/EI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=a2r9NKlhfwzKXpHhNPH9alTLDX8P8mf1mJxLYbCErn1uedIGo6QkaerYwlJM2TPlL Wuz58pzdiu/Yr5R6d3DDMrprR7qcGGT12h+EOWu9gGsGGYgR71XbEvkWQFLyMm1rOS i0+0fMA2Hen5Hx3uSc0j9oKNm4eKkAQAGN9d+HeKHZh3oBNB9CJ0D8ihiMb3zJlxlT AVEvDs9ywpq60qqZmmqzc2E1kcYpEAxkt6zn2ivivSCJBOB4m7emARuXX0EBMiKjvG NjMfr3ZkTDvD+AH7icDnbXj2FAubaeLJF88Qj+YtTX5RbPn6abuVXPxyYdhEl6nEjf YG6hE49VmNS9A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA9A3CAC5B8; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:24 +0800 Subject: [PATCH 11/19] arm64: dts: amlogic: A4: Add peripherals clock controller node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-a4_a5_add_clock_driver-v1-11-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=1947; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=WkZjCGYH9SRZ1p+CbboLb8KN0Yvea30tPFS+Yn032E8=; b=24BHjpOH4gCCvBgh+DjCK5+2l9sJd9v4b8UIh947+UdrksdwZhUuw12uWaJw/27TRTxRo5Ddb KHdpac5OKj9DyJkBJV814kMWQ5dG6ngI/Z2tXLhRKgltH8WEvNX+vCD X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the peripherals clock controller node for A4 SoC family. Signed-off-by: Chuan Liu --- arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 39 +++++++++++++++++++++++++= ++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-a4.dtsi index aca81e658654..3404358aff58 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include =20 / { cpus { @@ -83,6 +84,44 @@ scmi_clk: protocol@14 { }; =20 &apb { + clkc_periphs: clock-controller@0 { + compatible =3D "amlogic,a4-peripherals-clkc"; + reg =3D <0x0 0x0 0x0 0x20c>; + #clock-cells =3D <1>; + clocks =3D <&xtal>, + <&scmi_clk CLKID_OSC>, + <&scmi_clk CLKID_FIXED_PLL>, + <&scmi_clk CLKID_FCLK_DIV2>, + <&scmi_clk CLKID_FCLK_DIV2P5>, + <&scmi_clk CLKID_FCLK_DIV3>, + <&scmi_clk CLKID_FCLK_DIV4>, + <&scmi_clk CLKID_FCLK_DIV5>, + <&scmi_clk CLKID_FCLK_DIV7>, + <&clkc_pll CLKID_GP0_PLL>, + <&scmi_clk CLKID_GP1_PLL>, + <&clkc_pll CLKID_HIFI_PLL>, + <&scmi_clk CLKID_SYS_CLK>, + <&scmi_clk CLKID_AXI_CLK>, + <&scmi_clk CLKID_SYS_PLL_DIV16>, + <&scmi_clk CLKID_CPU_CLK_DIV16>; + clock-names =3D "xtal", + "oscin", + "fix", + "fdiv2", + "fdiv2p5", + "fdiv3", + "fdiv4", + "fdiv5", + "fdiv7", + "gp0", + "gp1", + "hifi", + "sysclk",s + "axiclk", + "sysplldiv16", + "cpudiv16"; + }; + reset: reset-controller@2000 { compatible =3D "amlogic,a4-reset", "amlogic,meson-s4-reset"; --=20 2.42.0 From nobody Wed Dec 17 14:13:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FC2A2F656B; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; cv=none; b=HRYitQvVsX/QdW4jMSS5um+OO4RXBM/S2sXc0XkOebXi9l4PvFSx6ZRZfU/8zPEjG6zKNi5wHpjWzppXSpE/LmfnG+kCll/GOSm7/T8CvITBiS9Qx0JRpVZ+5ejk34w4c0mcr1Pyyozx7jo+h9vczzPzLfiXtWXAyjQQYZGuAxA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; c=relaxed/simple; bh=y+/nG1RB4CcOjHU49MzledrxQ0x1bK5PWySm2xxXylU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Xb8CKvsuTGXPe3H32N9paHOALZRBhEfsDbyHYakirEu8yrq0y/1bj1m1baTKeuhufCT1AIFEAXAyGBVGCPh1H/drCrnntITUhKAq9hAtOqWyiDTTg3xU5Z95fCwZ4IIayzHm2vRiRviM7owfwmSYCzuetH098XStR/9ZJ/UzVv4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=d/dGqS9B; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="d/dGqS9B" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0F68AC19421; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225052; bh=y+/nG1RB4CcOjHU49MzledrxQ0x1bK5PWySm2xxXylU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=d/dGqS9BsH4ISHsdnjFt9pnaOCX24Sg+f1f9gVCnvtXfh1/Roma1f8N5D3hB16bHn TIqgRRcY3JIUAP0LOAjiGuu9ywpDHLn1aQ05R+5cFa3jvIIjVfFl5KAfjj7Ur4VD72 nNwLapvzTa/yziT+v0rIpvNV2+ZxEY/tksYn7q7mpkqxsIRz3VAmslc8MWfk0460KC T1nmktjLKMUWvwUh5nj1UG0bz6M/zM4xM2Rr2yHIYBOHAn+Yk4yJvPomV/t2w0+6Wz 2RWrbPvfLjzaoBZp5xAxgSavzKzVsfD18Nn1GMsdOnClWsmP/SCK/giw9bNABapRs1 WoVbVHDQKotCg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07783CAC5B9; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:25 +0800 Subject: [PATCH 12/19] dt-bindings: clock: Add Amlogic A5 SCMI clock controller support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-a4_a5_add_clock_driver-v1-12-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=2047; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=CUR2pdjRbzn6+DAqRfbcYQodptVVflwPa6cKLrjmKRk=; b=mNi+DwQap04YFOWpZvxQdv0PnR84ND8ajhtbq1nTfik0/qcmbdTbCUyL+SC8+DqnnzrhaYSQc h2xW+BQE8aKDDBn1nx3hFYwP4uEJsOgKWt6SPCM7DV9fmBnjR6+X/M7 X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the SCMI clock controller dt-bindings for the Amlogic A5 SoC family. Reviewed-by: Rob Herring (Arm) Co-developed-by: Xianwei Zhao Signed-off-by: Xianwei Zhao Signed-off-by: Chuan Liu --- include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 ++++++++++++++++++++= ++++ 1 file changed, 44 insertions(+) diff --git a/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h b/include/dt-= bindings/clock/amlogic,a5-scmi-clkc.h new file mode 100644 index 000000000000..1bf027d0110a --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu + */ + +#ifndef __AMLOGIC_A5_SCMI_CLKC_H +#define __AMLOGIC_A5_SCMI_CLKC_H + +#define CLKID_OSC 0 +#define CLKID_SYS_CLK 1 +#define CLKID_AXI_CLK 2 +#define CLKID_CPU_CLK 3 +#define CLKID_DSU_CLK 4 +#define CLKID_GP1_PLL 5 +#define CLKID_FIXED_PLL_DCO 6 +#define CLKID_FIXED_PLL 7 +#define CLKID_ACLKM 8 +#define CLKID_SYS_PLL_DIV16 9 +#define CLKID_CPU_CLK_DIV16 10 +#define CLKID_FCLK_50M_PREDIV 11 +#define CLKID_FCLK_50M_DIV 12 +#define CLKID_FCLK_50M 13 +#define CLKID_FCLK_DIV2_DIV 14 +#define CLKID_FCLK_DIV2 15 +#define CLKID_FCLK_DIV2P5_DIV 16 +#define CLKID_FCLK_DIV2P5 17 +#define CLKID_FCLK_DIV3_DIV 18 +#define CLKID_FCLK_DIV3 19 +#define CLKID_FCLK_DIV4_DIV 20 +#define CLKID_FCLK_DIV4 21 +#define CLKID_FCLK_DIV5_DIV 22 +#define CLKID_FCLK_DIV5 23 +#define CLKID_FCLK_DIV7_DIV 24 +#define CLKID_FCLK_DIV7 25 +#define CLKID_SYS_MMC_PCLK 26 +#define CLKID_SYS_CPU_CTRL 27 +#define CLKID_SYS_IRQ_CTRL 28 +#define CLKID_SYS_GIC 29 +#define CLKID_SYS_BIG_NIC 30 +#define CLKID_AXI_SYS_NIC 31 +#define CLKID_AXI_CPU_DMC 32 + +#endif /* __AMLOGIC_A5_SCMI_CLKC_H */ --=20 2.42.0 From nobody Wed Dec 17 14:13:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4079E2F60DA; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; cv=none; b=aZeo4ITWBsJ56cX+Upal1Z07akZCz5vna2JR+4q+KnW+pG3Suq/BaKDHFGA7qL5XjARdMmzHR6lx8175KwAB/IVI/Ai1L+iPLrokjPf4DkZJ/o4wk0uVx9kswWMlrijgBofD+OQMKzcFRZLnz90Sd3ZETYtnoIJssbdeIYoOMd8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; c=relaxed/simple; bh=iduM5ruKcSRbsgtSF/oCeeTRH74329Jq/IPAq89deCY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hCKABaoePqpyJf1QRoVobVkkuur9YYotXJrWZDD1moYb0YsJfJdmfWlkyMRwYGjt2W6FY3JsQYrMSG983IwWLmssCO7CV/V5YFCrSfbCMz/6gmsMrvExAy5tbEolrR7i1TtMGDfpOoRNmji3E/4BCAwTo/sz3+VBOfCfmRF/EIo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=p8iDqz0f; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="p8iDqz0f" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1F47EC116D0; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225052; bh=iduM5ruKcSRbsgtSF/oCeeTRH74329Jq/IPAq89deCY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=p8iDqz0fnW1jUh4EhX9OOdrEC/Dyk7YtxWm0izM/PeVAP9dQYTtLczt9S0HaXvybr Zb1notTRRwZSC8NG9sd1xwfrfUKkrJyiXXa7U5O0U7Un5cGkjElX9GHU/PrwgHHKqY YD9MeeIGucL0I5LyF1QrcSFMWEdzDkNBbzvvToTTivpMjDZmHMGyr8lwC7+mehyqzR dmuwVqyEb7SDHHXduMzRCqsbC3tpQIM2qNvbGu/USWdnmOiSlI6HR8I/BgpQcUa+6d 1NKtd4pNZFGwA769+sB9QSeqKHCXRpmxyOT3TNA3LaP2yN9sVNTUOIKZWeYNeuqr/V Pl5qLEa0HOguQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 175A9CAC5B8; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:26 +0800 Subject: [PATCH 13/19] dt-bindings: clock: Add Amlogic A5 PLL clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-a4_a5_add_clock_driver-v1-13-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=3305; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=FbJzu6MMV9K0oEojcZA0Oa8nUqpv/efWvnH7HSB/Xv4=; b=XDvBXuIBpVymQI5+i5A+XmRn9LpHbqiVtfZ/mfAirezMBw52LqbnDIVk4Nf2Klj2Cm6hoIYp7 PZjs/K76GiCCR8d5qG259i2jf9wnurGBzPSPOzNF4hsbMnCRigmjAuN X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the PLL clock controller dt-bindings for the Amlogic A5 SoC family. Reviewed-by: Rob Herring (Arm) Co-developed-by: Xianwei Zhao Signed-off-by: Xianwei Zhao Signed-off-by: Chuan Liu --- .../bindings/clock/amlogic,a5-pll-clkc.yaml | 63 ++++++++++++++++++= ++++ include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 +++++++++ 2 files changed, 87 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,a5-pll-clkc.ya= ml b/Documentation/devicetree/bindings/clock/amlogic,a5-pll-clkc.yaml new file mode 100644 index 000000000000..d74570a90926 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a5-pll-clkc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2024 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,a5-pll-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A5 series PLL Clock Controller + +maintainers: + - Chuan Liu + - Xianwei Zhao + +properties: + compatible: + const: amlogic,a5-pll-clkc + + reg: + maxItems: 1 + + clocks: + items: + - description: input oscillator + - description: input fix pll dco + - description: input fix pll + + clock-names: + items: + - const: xtal + - const: fix_dco + - const: fix + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include + apb { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@8000 { + compatible =3D "amlogic,a5-pll-clkc"; + reg =3D <0x0 0x8000 0x0 0x1a4>; + clocks =3D <&xtal>, + <&scmi_clk CLKID_FIXED_PLL_DCO>, + <&scmi_clk CLKID_FIXED_PLL>; + clock-names =3D "xtal", + "fix_dco", + "fix"; + #clock-cells =3D <1>; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,a5-pll-clkc.h b/include/dt-b= indings/clock/amlogic,a5-pll-clkc.h new file mode 100644 index 000000000000..a74c448a8d8a --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a5-pll-clkc.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu + */ + +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_A5_PLL_CLKC_H +#define _DT_BINDINGS_CLOCK_AMLOGIC_A5_PLL_CLKC_H + +#define CLKID_MPLL_PREDIV 0 +#define CLKID_MPLL0_DIV 1 +#define CLKID_MPLL0 2 +#define CLKID_MPLL1_DIV 3 +#define CLKID_MPLL1 4 +#define CLKID_MPLL2_DIV 5 +#define CLKID_MPLL2 6 +#define CLKID_MPLL3_DIV 7 +#define CLKID_MPLL3 8 +#define CLKID_GP0_PLL_DCO 9 +#define CLKID_GP0_PLL 10 +#define CLKID_HIFI_PLL_DCO 11 +#define CLKID_HIFI_PLL 12 + +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_A5_PLL_CLKC_H */ --=20 2.42.0 From nobody Wed Dec 17 14:13:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7800D2F7475; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; cv=none; b=DAuCpNYR5GhuoWacP9GApGQ+H75RcRWaK9hQtN49d2r/ZWqNucndR29nADd/yMyuTNAdz0zotN7GJH9dRDf3g9UZeqXUfBrPfehwxWVDuEqLSz1LMrAGK9BEraQZ9DR1rd3yeU8AEwwtNgAAFNs46IMalzISSA1+18PBRn9/gAs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; c=relaxed/simple; bh=vqbss3GMqYKyjAUeXpUSBjKgviFCWxod5+9aHRq1ztY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XFrRdCR8YSbWnJ4iIArOaZ/06SyQtuSdzMD88Qgrvy5IsCa+ublGCqWc4fioHbHlLaOBfBL0HLHww6sWEL4ES+PNnOYHUHY4WVPZXuN2vVZO/S6RoYJHYG++4HmmJ1M8x8FNYjCZ2XmjnB3Bz0CV7gj/UeFb/ybr6EapNvA884E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UrtiKNLm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UrtiKNLm" Received: by smtp.kernel.org (Postfix) with ESMTPS id 2E725C4CEF7; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225052; bh=vqbss3GMqYKyjAUeXpUSBjKgviFCWxod5+9aHRq1ztY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=UrtiKNLmevBL/yImcd8DWr64Y5ipOKvdUoikcSGIlcF251jd87+RUtk6bQMqycKXV bmuXdSv5N88P/buACUSlCbLZdOC0GONJxK3lGvjl304ow7CN1mFrqicA0YmnWuDLj4 03CdS45TDPG1TXqk1UvAKAF9GpmSIAQ9JffQYWJTpfoErzyxv87q7v9f6tdPiaVyEe dujz4excsytn3atUN/dc1ygCpEV+mkaZzLWHqH5FamobksD4sh7eALRKboqh4THrVB ZMFQA9UsqkqMNzfjLVl2LpdZu+uGB89WjnBoS8Lcw+MeVmkH1ql6SkOpi+8WmgzfPq XHWo5TYew6YDg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25FB2CCA472; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:27 +0800 Subject: [PATCH 14/19] dt-bindings: clock: Add Amlogic A5 peripherals clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-a4_a5_add_clock_driver-v1-14-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=9596; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=LDsJSfffZZmihBCb3jZySU47D3GfC2AzT2yzTyvoxfo=; b=rmZ04qz/v20Bq80D/CQHFlQpXL5aIoNo9m68Uaakwiyltwicyc0kh3mPPQ8MSBbjelG+GTY+e N7TX5/vsD6jChSOPBOl4Apye9J+TAt3dmwSg0Vy2rL8tSYA0isJTumY X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the peripherals clock controller dt-bindings for the Amlogic A5 SoC family. Reviewed-by: Rob Herring (Arm) Co-developed-by: Xianwei Zhao Signed-off-by: Xianwei Zhao Signed-off-by: Chuan Liu --- .../clock/amlogic,a5-peripherals-clkc.yaml | 134 +++++++++++++++++= ++++ .../clock/amlogic,a5-peripherals-clkc.h | 132 +++++++++++++++++= +++ 2 files changed, 266 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,a5-peripherals= -clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a5-peripherals= -clkc.yaml new file mode 100644 index 000000000000..88d71d9a72ea --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a5-peripherals-clkc.y= aml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2024 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,a5-peripherals-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A5 series Peripheral Clock Controller + +maintainers: + - Xianwei Zhao + - Chuan Liu + +properties: + compatible: + const: amlogic,a5-peripherals-clkc + + reg: + maxItems: 1 + + clocks: + minItems: 18 + items: + - description: input oscillator + - description: input oscillators multiplexer + - description: input fix pll + - description: input fclk div 2 + - description: input fclk div 2p5 + - description: input fclk div 3 + - description: input fclk div 4 + - description: input fclk div 5 + - description: input fclk div 7 + - description: input mpll2 + - description: input mpll3 + - description: input gp0 pll + - description: input gp1 pll + - description: input hifi pll + - description: input sys clk + - description: input axi clk + - description: input sys pll div 16 + - description: input cpu clk div 16 + - description: input pad clock for rtc clk (optional) + - description: input ddr pll (optional) + - description: input source from clk-measure (optional) + - description: input rtc pll (optional) + + clock-names: + minItems: 18 + items: + - const: xtal + - const: oscin + - const: fix + - const: fdiv2 + - const: fdiv2p5 + - const: fdiv3 + - const: fdiv4 + - const: fdiv5 + - const: fdiv7 + - const: mpll2 + - const: mpll3 + - const: gp0 + - const: gp1 + - const: hifi + - const: sysclk + - const: axiclk + - const: sysplldiv16 + - const: cpudiv16 + - const: pad_osc + - const: ddr + - const: clkmsr + - const: rtc + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include + #include + apb { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@0 { + compatible =3D "amlogic,a5-peripherals-clkc"; + reg =3D <0x0 0x0 0x0 0x224>; + #clock-cells =3D <1>; + clocks =3D <&xtal>, + <&scmi_clk CLKID_OSC>, + <&scmi_clk CLKID_FIXED_PLL>, + <&scmi_clk CLKID_FCLK_DIV2>, + <&scmi_clk CLKID_FCLK_DIV2P5>, + <&scmi_clk CLKID_FCLK_DIV3>, + <&scmi_clk CLKID_FCLK_DIV4>, + <&scmi_clk CLKID_FCLK_DIV5>, + <&scmi_clk CLKID_FCLK_DIV7>, + <&clkc_pll CLKID_MPLL2>, + <&clkc_pll CLKID_MPLL3>, + <&clkc_pll CLKID_GP0_PLL>, + <&scmi_clk CLKID_GP1_PLL>, + <&clkc_pll CLKID_HIFI_PLL>, + <&scmi_clk CLKID_SYS_CLK>, + <&scmi_clk CLKID_AXI_CLK>, + <&scmi_clk CLKID_SYS_PLL_DIV16>, + <&scmi_clk CLKID_CPU_CLK_DIV16>; + clock-names =3D "xtal", + "oscin", + "fix", + "fdiv2", + "fdiv2p5", + "fdiv3", + "fdiv4", + "fdiv5", + "fdiv7", + "mpll2", + "mpll3", + "gp0", + "gp1", + "hifi", + "sysclk", + "axiclk", + "sysplldiv16", + "cpudiv16"; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,a5-peripherals-clkc.h b/incl= ude/dt-bindings/clock/amlogic,a5-peripherals-clkc.h new file mode 100644 index 000000000000..b8a68b7f29dc --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a5-peripherals-clkc.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu + */ + +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_A5_PERIPHERALS_CLKC_H +#define _DT_BINDINGS_CLOCK_AMLOGIC_A5_PERIPHERALS_CLKC_H + +#define CLKID_RTC_DUALDIV_CLKIN 0 +#define CLKID_RTC_DUALDIV 1 +#define CLKID_RTC_DUALDIV_SEL 2 +#define CLKID_RTC_DUALDIV_CLKOUT 3 +#define CLKID_RTC_CLK 4 +#define CLKID_SYS_RESET_CTRL 5 +#define CLKID_SYS_PWR_CTRL 6 +#define CLKID_SYS_PAD_CTRL 7 +#define CLKID_SYS_CTRL 8 +#define CLKID_SYS_TS_PLL 9 +#define CLKID_SYS_DEV_ARB 10 +#define CLKID_SYS_MAILBOX 11 +#define CLKID_SYS_JTAG_CTRL 12 +#define CLKID_SYS_IR_CTRL 13 +#define CLKID_SYS_MSR_CLK 14 +#define CLKID_SYS_ROM 15 +#define CLKID_SYS_CPU_ARB 16 +#define CLKID_SYS_RSA 17 +#define CLKID_SYS_SARADC 18 +#define CLKID_SYS_STARTUP 19 +#define CLKID_SYS_SECURE 20 +#define CLKID_SYS_SPIFC 21 +#define CLKID_SYS_DSPA 22 +#define CLKID_SYS_NNA 23 +#define CLKID_SYS_ETH_MAC 24 +#define CLKID_SYS_RAMA 25 +#define CLKID_SYS_RAMB 26 +#define CLKID_SYS_AUDIO_TOP 27 +#define CLKID_SYS_AUDIO_VAD 28 +#define CLKID_SYS_USB 29 +#define CLKID_SYS_SD_EMMC_A 30 +#define CLKID_SYS_SD_EMMC_C 31 +#define CLKID_SYS_PWM_AB 32 +#define CLKID_SYS_PWM_CD 33 +#define CLKID_SYS_PWM_EF 34 +#define CLKID_SYS_PWM_GH 35 +#define CLKID_SYS_SPICC_1 36 +#define CLKID_SYS_SPICC_0 37 +#define CLKID_SYS_UART_A 38 +#define CLKID_SYS_UART_B 39 +#define CLKID_SYS_UART_C 40 +#define CLKID_SYS_UART_D 41 +#define CLKID_SYS_UART_E 42 +#define CLKID_SYS_I2C_M_A 43 +#define CLKID_SYS_I2C_M_B 44 +#define CLKID_SYS_I2C_M_C 45 +#define CLKID_SYS_I2C_M_D 46 +#define CLKID_SYS_RTC 47 +#define CLKID_AXI_AUDIO_VAD 48 +#define CLKID_AXI_AUDIO_TOP 49 +#define CLKID_AXI_RAMB 50 +#define CLKID_AXI_RAMA 51 +#define CLKID_AXI_NNA 52 +#define CLKID_AXI_DEV1_DMC 53 +#define CLKID_AXI_DEV0_DMC 54 +#define CLKID_AXI_DSP_DMC 55 +#define CLKID_12_24M_IN 56 +#define CLKID_12M_24M 57 +#define CLKID_FCLK_25M_DIV 58 +#define CLKID_FCLK_25M 59 +#define CLKID_GEN_SEL 60 +#define CLKID_GEN_DIV 61 +#define CLKID_GEN 62 +#define CLKID_SARADC_SEL 63 +#define CLKID_SARADC_DIV 64 +#define CLKID_SARADC 65 +#define CLKID_PWM_A_SEL 66 +#define CLKID_PWM_A_DIV 67 +#define CLKID_PWM_A 68 +#define CLKID_PWM_B_SEL 69 +#define CLKID_PWM_B_DIV 70 +#define CLKID_PWM_B 71 +#define CLKID_PWM_C_SEL 72 +#define CLKID_PWM_C_DIV 73 +#define CLKID_PWM_C 74 +#define CLKID_PWM_D_SEL 75 +#define CLKID_PWM_D_DIV 76 +#define CLKID_PWM_D 77 +#define CLKID_PWM_E_SEL 78 +#define CLKID_PWM_E_DIV 79 +#define CLKID_PWM_E 80 +#define CLKID_PWM_F_SEL 81 +#define CLKID_PWM_F_DIV 82 +#define CLKID_PWM_F 83 +#define CLKID_PWM_G_SEL 84 +#define CLKID_PWM_G_DIV 85 +#define CLKID_PWM_G 86 +#define CLKID_PWM_H_SEL 87 +#define CLKID_PWM_H_DIV 88 +#define CLKID_PWM_H 89 +#define CLKID_SPICC_0_SEL 90 +#define CLKID_SPICC_0_DIV 91 +#define CLKID_SPICC_0 92 +#define CLKID_SPICC_1_SEL 93 +#define CLKID_SPICC_1_DIV 94 +#define CLKID_SPICC_1 95 +#define CLKID_SD_EMMC_A_SEL 96 +#define CLKID_SD_EMMC_A_DIV 97 +#define CLKID_SD_EMMC_A 98 +#define CLKID_SD_EMMC_C_SEL 99 +#define CLKID_SD_EMMC_C_DIV 100 +#define CLKID_SD_EMMC_C 101 +#define CLKID_TS_DIV 102 +#define CLKID_TS 103 +#define CLKID_ETH_125M_DIV 104 +#define CLKID_ETH_125M 105 +#define CLKID_ETH_RMII_DIV 106 +#define CLKID_ETH_RMII 107 +#define CLKID_DSPA_0_SEL 108 +#define CLKID_DSPA_0_DIV 109 +#define CLKID_DSPA_0 110 +#define CLKID_DSPA_1_SEL 111 +#define CLKID_DSPA_1_DIV 112 +#define CLKID_DSPA_1 113 +#define CLKID_DSPA 114 +#define CLKID_NNA_CORE_SEL 115 +#define CLKID_NNA_CORE_DIV 116 +#define CLKID_NNA_CORE 117 +#define CLKID_NNA_AXI_SEL 118 +#define CLKID_NNA_AXI_DIV 119 +#define CLKID_NNA_AXI 120 + +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_A5_PERIPHERALS_CLKC_H */ --=20 2.42.0 From nobody Wed Dec 17 14:13:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6511F2F7461; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; cv=none; b=o3p+zPKYXkRQpCVbV8Jb28gcRuxbXVMDdhtC7LTN6/aAh2O6qM05iAbWi+NszkriNQrKoaFepr08IK6GAzJsXjJN7+q5EtyGSPDCiyBfUTT8f++GasgS7/0EtXwydIK30OyzWvCjVaWKAqCACjMxiUlMSpUThFhU4iKT0rlyN+U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; c=relaxed/simple; bh=JhV6skffu+U/f+2pBI+0199BgRiLUbf/66Men8rpJ9o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=D0vugI150G+HxtuVEkBYR3rCEVbmUPG5EpyNjtn/wEfAqsw2yv20LtWrJziygeDjD88QAnf7jL0ChPKHAi8D0fRm8Zb+u62M89rOZJW5YGESkboNlLTmlAwmlDg6EUP54yszmVxvs0ejoU9QknuVGHVK2B3rzlsMtXQVxMhzU2Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TYSzv/FH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TYSzv/FH" Received: by smtp.kernel.org (Postfix) with ESMTPS id 411CFC2BCB0; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225052; bh=JhV6skffu+U/f+2pBI+0199BgRiLUbf/66Men8rpJ9o=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=TYSzv/FHJ6jv2cSohc4wT8dGy533RYKQLuYlTscYRHLpLJ/2ibgJd5tDuupIZYVYf 0dfoubZDQmcK+rxo96GZ5i5Lq8yhvtceHPIXLYaAFUxUiY5vYDuIrJ9Cy6YpO4HwxO LJbVRw6Izqvl1PFljpd7c6OEB7aXkQHuAea/udhg5vfeBIzoXuijXaXAXbUw3mhcme hrWAGMdNkJFNfOgmVf0DjsAPyI0vCVYeNOFK4gnu7KS7qqBnXgzW88NhJFn0tvxCDu PyiWZNja1OI3SbqiRDg2wVV934710o8FM27ghrz/e73RMM528AgWRMPrj2W64hl0AS Gz77WSwBMkAbg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 363D7CCA470; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:28 +0800 Subject: [PATCH 15/19] clk: amlogic: Add A5 PLL clock controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-a4_a5_add_clock_driver-v1-15-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=13661; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=IAgkTKQ5BLzjttr74FEQCH4E1ZalhIwg2M7io4Tt3jc=; b=Z0WVdsIso0VbUVCLhVeyWbbM1ouMzoGxNvX6+MkS5nXukHaErVZvzjTxRuxEX25QZjVLTWg2O 1r++KjHWeRiBTXDjnZnt4hGgWWir+0Dimni5GN+RAO80cT2qgdsIKip X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the PLL clock controller driver for the Amlogic A5 SoC family. Co-developed-by: Xianwei Zhao Signed-off-by: Xianwei Zhao Signed-off-by: Chuan Liu --- drivers/clk/meson/Kconfig | 14 ++ drivers/clk/meson/Makefile | 1 + drivers/clk/meson/a5-pll.c | 476 +++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 491 insertions(+) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 860625ca6e9b..db4b98abf4f4 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -158,6 +158,20 @@ config COMMON_CLK_A4_PERIPHERALS Support for the Peripherals clock controller on Amlogic BA40X device, AKA A4. Say Y if you want the peripherals clock to work. =20 +config COMMON_CLK_A5_PLL + tristate "Amlogic A5 PLL clock controller" + depends on ARM64 + default ARCH_MESON + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_PLL + select COMMON_CLK_MESON_MPLL + select COMMON_CLK_MESON_CLKC_UTILS + imply COMMON_CLK_SCMI + help + Support for the PLL clock controller on Amlogic A113X2 device, AKA A5. + Say Y if you want the board to work, because PLLs are the parent + of most peripherals. + config COMMON_CLK_C3_PLL tristate "Amlogic C3 PLL clock controller" depends on ARM64 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 88f6b336a6ca..ff73d2486f05 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_COMMON_CLK_A1_PLL) +=3D a1-pll.o obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) +=3D a1-peripherals.o obj-$(CONFIG_COMMON_CLK_A4_PLL) +=3D a4-pll.o obj-$(CONFIG_COMMON_CLK_A4_PERIPHERALS) +=3D a4-peripherals.o +obj-$(CONFIG_COMMON_CLK_A5_PLL) +=3D a5-pll.o obj-$(CONFIG_COMMON_CLK_C3_PLL) +=3D c3-pll.o obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) +=3D c3-peripherals.o obj-$(CONFIG_COMMON_CLK_GXBB) +=3D gxbb.o gxbb-aoclk.o diff --git a/drivers/clk/meson/a5-pll.c b/drivers/clk/meson/a5-pll.c new file mode 100644 index 000000000000..1789a7e6470d --- /dev/null +++ b/drivers/clk/meson/a5-pll.c @@ -0,0 +1,476 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Amlogic A5 PLL Controller Driver + * + * Copyright (c) 2024-2025 Amlogic, inc. + * Author: Chuan Liu + */ + +#include +#include +#include "clk-regmap.h" +#include "clk-pll.h" +#include "clk-mpll.h" +#include "meson-clkc-utils.h" +#include + +#define GP0PLL_CTRL0 0x80 +#define GP0PLL_CTRL1 0x84 +#define GP0PLL_CTRL2 0x88 +#define GP0PLL_CTRL3 0x8c +#define GP0PLL_CTRL4 0x90 +#define GP0PLL_CTRL5 0x94 +#define GP0PLL_CTRL6 0x98 +#define HIFIPLL_CTRL0 0x100 +#define HIFIPLL_CTRL1 0x104 +#define HIFIPLL_CTRL2 0x108 +#define HIFIPLL_CTRL3 0x10c +#define HIFIPLL_CTRL4 0x110 +#define HIFIPLL_CTRL5 0x114 +#define HIFIPLL_CTRL6 0x118 +#define MPLL_CTRL0 0x180 +#define MPLL_CTRL1 0x184 +#define MPLL_CTRL2 0x188 +#define MPLL_CTRL3 0x18c +#define MPLL_CTRL4 0x190 +#define MPLL_CTRL5 0x194 +#define MPLL_CTRL6 0x198 +#define MPLL_CTRL7 0x19c +#define MPLL_CTRL8 0x1a0 + +static struct clk_fixed_factor a5_mpll_prediv =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll_prediv", + .ops =3D &clk_fixed_factor_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fix_dco" + }, + .num_parents =3D 1, + }, +}; + +static const struct reg_sequence a5_mpll0_init_regs[] =3D { + { .reg =3D MPLL_CTRL2, .def =3D 0x40000033 }, +}; + +static struct clk_regmap a5_mpll0_div =3D { + .data =3D &(struct meson_clk_mpll_data){ + .sdm =3D { + .reg_off =3D MPLL_CTRL1, + .shift =3D 0, + .width =3D 14, + }, + .sdm_en =3D { + .reg_off =3D MPLL_CTRL1, + .shift =3D 30, + .width =3D 1, + }, + .n2 =3D { + .reg_off =3D MPLL_CTRL1, + .shift =3D 20, + .width =3D 9, + }, + .ssen =3D { + .reg_off =3D MPLL_CTRL1, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D a5_mpll0_init_regs, + .init_count =3D ARRAY_SIZE(a5_mpll0_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll0_div", + .ops =3D &meson_clk_mpll_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_mpll_prediv.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_mpll0 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MPLL_CTRL1, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll0", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { &a5_mpll0_div.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence a5_mpll1_init_regs[] =3D { + { .reg =3D MPLL_CTRL4, .def =3D 0x40000033 }, +}; + +static struct clk_regmap a5_mpll1_div =3D { + .data =3D &(struct meson_clk_mpll_data){ + .sdm =3D { + .reg_off =3D MPLL_CTRL3, + .shift =3D 0, + .width =3D 14, + }, + .sdm_en =3D { + .reg_off =3D MPLL_CTRL3, + .shift =3D 30, + .width =3D 1, + }, + .n2 =3D { + .reg_off =3D MPLL_CTRL3, + .shift =3D 20, + .width =3D 9, + }, + .ssen =3D { + .reg_off =3D MPLL_CTRL3, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D a5_mpll1_init_regs, + .init_count =3D ARRAY_SIZE(a5_mpll1_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll1_div", + .ops =3D &meson_clk_mpll_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_mpll_prediv.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_mpll1 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MPLL_CTRL3, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "a5_mpll1", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { &a5_mpll1_div.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence a5_mpll2_init_regs[] =3D { + { .reg =3D MPLL_CTRL6, .def =3D 0x40000033 }, +}; + +static struct clk_regmap a5_mpll2_div =3D { + .data =3D &(struct meson_clk_mpll_data){ + .sdm =3D { + .reg_off =3D MPLL_CTRL5, + .shift =3D 0, + .width =3D 14, + }, + .sdm_en =3D { + .reg_off =3D MPLL_CTRL5, + .shift =3D 30, + .width =3D 1, + }, + .n2 =3D { + .reg_off =3D MPLL_CTRL5, + .shift =3D 20, + .width =3D 9, + }, + .ssen =3D { + .reg_off =3D MPLL_CTRL5, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D a5_mpll2_init_regs, + .init_count =3D ARRAY_SIZE(a5_mpll2_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll2_div", + .ops =3D &meson_clk_mpll_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_mpll_prediv.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_mpll2 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MPLL_CTRL5, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll2", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { &a5_mpll2_div.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence a5_mpll3_init_regs[] =3D { + { .reg =3D MPLL_CTRL8, .def =3D 0x40000033 }, +}; + +static struct clk_regmap a5_mpll3_div =3D { + .data =3D &(struct meson_clk_mpll_data){ + .sdm =3D { + .reg_off =3D MPLL_CTRL7, + .shift =3D 0, + .width =3D 14, + }, + .sdm_en =3D { + .reg_off =3D MPLL_CTRL7, + .shift =3D 30, + .width =3D 1, + }, + .n2 =3D { + .reg_off =3D MPLL_CTRL7, + .shift =3D 20, + .width =3D 9, + }, + .ssen =3D { + .reg_off =3D MPLL_CTRL7, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D a5_mpll3_init_regs, + .init_count =3D ARRAY_SIZE(a5_mpll3_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll3_div", + .ops =3D &meson_clk_mpll_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_mpll_prediv.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_mpll3 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MPLL_CTRL7, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll3", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { &a5_mpll3_div.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence a5_gp0_init_regs[] =3D { + { .reg =3D GP0PLL_CTRL3, .def =3D 0x6a295c00 }, + { .reg =3D GP0PLL_CTRL4, .def =3D 0x65771290 }, + { .reg =3D GP0PLL_CTRL5, .def =3D 0x3927200a }, + { .reg =3D GP0PLL_CTRL6, .def =3D 0x54540000 } +}; + +static const struct pll_mult_range a5_gp0_pll_mult_range =3D { + .min =3D 125, + .max =3D 250, +}; + +static struct clk_regmap a5_gp0_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data) { + .en =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .frac =3D { + .reg_off =3D GP0PLL_CTRL1, + .shift =3D 0, + .width =3D 17, + }, + .n =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .l =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .range =3D &a5_gp0_pll_mult_range, + .init_regs =3D a5_gp0_init_regs, + .init_count =3D ARRAY_SIZE(a5_gp0_init_regs), + .frac_max =3D 100000, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gp0_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +/* The maximum frequency divider supports is 32, not 128(2^7) */ +static const struct clk_div_table a5_gp0_pll_od_table[] =3D { + { 0, 1 }, + { 1, 2 }, + { 2, 4 }, + { 3, 8 }, + { 4, 16 }, + { 5, 32 }, + { /* sentinel */ } +}; + +static struct clk_regmap a5_gp0_pll =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D GP0PLL_CTRL0, + .shift =3D 16, + .width =3D 3, + .table =3D a5_gp0_pll_od_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gp0_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_gp0_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence a5_hifi_init_regs[] =3D { + { .reg =3D HIFIPLL_CTRL3, .def =3D 0x6a285c00 }, + { .reg =3D HIFIPLL_CTRL4, .def =3D 0x65771290 }, + { .reg =3D HIFIPLL_CTRL5, .def =3D 0x3927200a }, + { .reg =3D HIFIPLL_CTRL6, .def =3D 0x56540000 } +}; + +static const struct pll_mult_range a5_hifi_pll_mult_range =3D { + .min =3D 125, + .max =3D 250, +}; + +static struct clk_regmap a5_hifi_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data) { + .en =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .frac =3D { + .reg_off =3D HIFIPLL_CTRL1, + .shift =3D 0, + .width =3D 17, + }, + .n =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .l =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .range =3D &a5_hifi_pll_mult_range, + .init_regs =3D a5_hifi_init_regs, + .init_count =3D ARRAY_SIZE(a5_hifi_init_regs), + .frac_max =3D 100000, + .flags =3D CLK_MESON_PLL_ROUND_CLOSEST, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hifi_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_hifi_pll =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D HIFIPLL_CTRL0, + .shift =3D 16, + .width =3D 2, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hifi_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_hifi_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_hw *a5_pll_hw_clks[] =3D { + [CLKID_MPLL_PREDIV] =3D &a5_mpll_prediv.hw, + [CLKID_MPLL0_DIV] =3D &a5_mpll0_div.hw, + [CLKID_MPLL0] =3D &a5_mpll0.hw, + [CLKID_MPLL1_DIV] =3D &a5_mpll1_div.hw, + [CLKID_MPLL1] =3D &a5_mpll1.hw, + [CLKID_MPLL2_DIV] =3D &a5_mpll2_div.hw, + [CLKID_MPLL2] =3D &a5_mpll2.hw, + [CLKID_MPLL3_DIV] =3D &a5_mpll3_div.hw, + [CLKID_MPLL3] =3D &a5_mpll3.hw, + [CLKID_GP0_PLL_DCO] =3D &a5_gp0_pll_dco.hw, + [CLKID_GP0_PLL] =3D &a5_gp0_pll.hw, + [CLKID_HIFI_PLL_DCO] =3D &a5_hifi_pll_dco.hw, + [CLKID_HIFI_PLL] =3D &a5_hifi_pll.hw +}; + +static const struct meson_clkc_data a5_pll_clkc_data =3D { + .hw_clks =3D { + .hws =3D a5_pll_hw_clks, + .num =3D ARRAY_SIZE(a5_pll_hw_clks), + }, +}; + +static const struct of_device_id a5_pll_clkc_match_table[] =3D { + { + .compatible =3D "amlogic,a5-pll-clkc", + .data =3D &a5_pll_clkc_data, + }, + {} +}; +MODULE_DEVICE_TABLE(of, a5_pll_clkc_match_table); + +static struct platform_driver a5_pll_clkc_driver =3D { + .probe =3D meson_clkc_mmio_probe, + .driver =3D { + .name =3D "a5-pll-clkc", + .of_match_table =3D a5_pll_clkc_match_table, + }, +}; +module_platform_driver(a5_pll_clkc_driver); + +MODULE_DESCRIPTION("Amlogic A5 PLL Clock Controller driver"); +MODULE_AUTHOR("Chuan Liu "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("CLK_MESON"); --=20 2.42.0 From nobody Wed Dec 17 14:13:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F0802F747C; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; cv=none; b=BY2E3SlIbjPyPv0BS+bFtW+XVc5mvdJKuBgR8dLe9mhB3rgo+AU4d8OU7h5SiL2m4pU/521XR1mo/hkhlcHXu8qqKluQsLD/+Rj76Z1/8XqE+uXl/MzJi2fw16OKqxv0IjMRyP9OfeeOJlKrwvNxOcY3S6w8KwsCt7UjgWB5nrc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; c=relaxed/simple; bh=oh4PASq7xylO3BBtX+WnDud/YQdsjyjmr7Yp6EcSjUk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nDyi3Cy/axBWtyGJM6WAiJ1X3aPCezQSvPa74CrF0iz5L5MVbrRUUUOF+ubwZCBORJNsQcf/2dQWJhb5eSPolJzujkL57meOAAazAlzDxHMgeUFQxGfncGPEUEQBUerqnB7DUPu1VTDcNoAcfR/xEY6XV/YM21Pqjc5A+59BAno= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OhIEuEq9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OhIEuEq9" Received: by smtp.kernel.org (Postfix) with ESMTPS id 564B2C2BCB1; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225052; bh=oh4PASq7xylO3BBtX+WnDud/YQdsjyjmr7Yp6EcSjUk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=OhIEuEq9Uo8HaiLRTAhG1VFViZayJv/tQX1/2fcOPHmbqAQAYlZfzTaVsc8MueDNv P5UYWXYwZKJdCOQ+no8K3DtiLFLGq+UKe0dc0k392+qYSdOdI9z9UrDHfBnZ+1LieZ ItmfBTqbBfpBcgyMny+Nf5joVDYn3rgm/BHp3GZMfahlgcCWIhzDWEb5p89bQjPZXR tfZ0ibcXT6wz9CAVAHOt+kBENZyixG/vIGkXIEkuFO42l2WoHUaD99VtSCs3ATgxk8 QOYXWDACnQ7UKMqOIJyRM6jAmQpFruVsHeeECKWi64o+OSRuLQWrlfNrFskjzZTPIu 8lWvlmSol4G+w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46E38CCA474; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:29 +0800 Subject: [PATCH 16/19] clk: amlogic: Add A5 clock peripherals controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-a4_a5_add_clock_driver-v1-16-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=30160; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=KeBxst5q1bZnGWsto6J1+CBIkEmgVhOABad3e1K1508=; b=CFfqtg+5M3qxmQ2Zcv522xtv3FT9zUURitpPtzBGNQ3LKfaIzcP3D9vVOvUgaDvFmdMWDKO2C R+M7D0wORm2A7gzI6PkWvafVbKlnrohqfboG2TF65zqNiO/rJF7eKu9 X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the peripherals clock controller driver for the Amlogic A5 SoC family. Co-developed-by: Xianwei Zhao Signed-off-by: Xianwei Zhao Signed-off-by: Chuan Liu --- drivers/clk/meson/Kconfig | 13 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/a5-peripherals.c | 883 +++++++++++++++++++++++++++++++++= ++++ 3 files changed, 897 insertions(+) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index db4b98abf4f4..eae9386d8e51 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -172,6 +172,19 @@ config COMMON_CLK_A5_PLL Say Y if you want the board to work, because PLLs are the parent of most peripherals. =20 +config COMMON_CLK_A5_PERIPHERALS + tristate "Amlogic A5 peripherals clock controller" + depends on ARM64 + default ARCH_MESON + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_DUALDIV + select COMMON_CLK_MESON_CLKC_UTILS + imply COMMON_CLK_SCMI + imply COMMON_CLK_A5_PLL + help + Support for the Peripherals clock controller on Amlogic A113X2 device, + AKA A5. Say Y if you want the peripherals clock to work. + config COMMON_CLK_C3_PLL tristate "Amlogic C3 PLL clock controller" depends on ARM64 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index ff73d2486f05..15001947ba1f 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) +=3D a1-periphera= ls.o obj-$(CONFIG_COMMON_CLK_A4_PLL) +=3D a4-pll.o obj-$(CONFIG_COMMON_CLK_A4_PERIPHERALS) +=3D a4-peripherals.o obj-$(CONFIG_COMMON_CLK_A5_PLL) +=3D a5-pll.o +obj-$(CONFIG_COMMON_CLK_A5_PERIPHERALS) +=3D a5-peripherals.o obj-$(CONFIG_COMMON_CLK_C3_PLL) +=3D c3-pll.o obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) +=3D c3-peripherals.o obj-$(CONFIG_COMMON_CLK_GXBB) +=3D gxbb.o gxbb-aoclk.o diff --git a/drivers/clk/meson/a5-peripherals.c b/drivers/clk/meson/a5-peri= pherals.c new file mode 100644 index 000000000000..eca9f3dcc256 --- /dev/null +++ b/drivers/clk/meson/a5-peripherals.c @@ -0,0 +1,883 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Amlogic A5 Peripherals Clock Controller Driver + * + * Copyright (c) 2024-2025 Amlogic, inc. + * Author: Chuan Liu + */ + +#include +#include +#include "clk-regmap.h" +#include "clk-dualdiv.h" +#include "meson-clkc-utils.h" +#include + +#define RTC_BY_OSCIN_CTRL0 0x8 +#define RTC_BY_OSCIN_CTRL1 0xc +#define RTC_CTRL 0x10 +#define SYS_CLK_EN0_REG0 0x44 +#define SYS_CLK_EN0_REG1 0x48 +#define DSPA_CLK_CTRL0 0x9c +#define CLK12_24_CTRL 0xa8 +#define AXI_CLK_EN0 0xac +#define TS_CLK_CTRL 0x158 +#define ETH_CLK_CTRL 0x164 +#define NAND_CLK_CTRL 0x168 +#define SD_EMMC_CLK_CTRL 0x16c +#define SPICC_CLK_CTRL 0x174 +#define GEN_CLK_CTRL 0x178 +#define SAR_CLK_CTRL0 0x17c +#define PWM_CLK_AB_CTRL 0x180 +#define PWM_CLK_CD_CTRL 0x184 +#define PWM_CLK_EF_CTRL 0x188 +#define PWM_CLK_GH_CTRL 0x18c +#define NNA_CLK_CNTL 0x220 + +static struct clk_regmap a5_rtc_dualdiv_clkin =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D RTC_BY_OSCIN_CTRL0, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_dualdiv_clkin", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "oscin", + }, + .num_parents =3D 1, + }, +}; + +static const struct meson_clk_dualdiv_param a5_rtc_dualdiv_table[] =3D { + { 733, 732, 8, 11, 1 }, + { /* sentinel */ } +}; + +static struct clk_regmap a5_rtc_dualdiv =3D { + .data =3D &(struct meson_clk_dualdiv_data) { + .n1 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL0, + .shift =3D 0, + .width =3D 12, + }, + .n2 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL0, + .shift =3D 12, + .width =3D 12, + }, + .m1 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL1, + .shift =3D 0, + .width =3D 12, + }, + .m2 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL1, + .shift =3D 12, + .width =3D 12, + }, + .dual =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .table =3D a5_rtc_dualdiv_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_dualdiv", + .ops =3D &meson_clk_dualdiv_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_rtc_dualdiv_clkin.hw + }, + .num_parents =3D 1, + }, +}; + +static const struct clk_parent_data a5_rtc_dualdiv_parent_data[] =3D { + { .hw =3D &a5_rtc_dualdiv.hw }, + { .hw =3D &a5_rtc_dualdiv_clkin.hw } +}; + +static struct clk_regmap a5_rtc_dualdiv_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D RTC_BY_OSCIN_CTRL1, + .mask =3D 0x1, + .shift =3D 24, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_dualdiv_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D a5_rtc_dualdiv_parent_data, + .num_parents =3D ARRAY_SIZE(a5_rtc_dualdiv_parent_data), + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a5_rtc_dualdiv_clkout =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D RTC_BY_OSCIN_CTRL0, + .bit_idx =3D 30, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_dualdiv_clkout", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_rtc_dualdiv_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data a5_rtc_clk_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .hw =3D &a5_rtc_dualdiv_clkout.hw }, + { .fw_name =3D "pad_osc" } +}; + +static struct clk_regmap a5_rtc_clk =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D RTC_CTRL, + .mask =3D 0x3, + .shift =3D 0, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_clk", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D a5_rtc_clk_parent_data, + .num_parents =3D ARRAY_SIZE(a5_rtc_clk_parent_data), + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +#define A5_PCLK(_name, _reg, _bit, _pdata, _flags) \ +struct clk_regmap a5_##_name =3D { \ + .data =3D &(struct clk_regmap_gate_data) { \ + .offset =3D (_reg), \ + .bit_idx =3D (_bit), \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name, \ + .ops =3D &clk_regmap_gate_ops, \ + .parent_data =3D (_pdata), \ + .num_parents =3D 1, \ + .flags =3D (_flags), \ + }, \ +} + +static const struct clk_parent_data a5_sys_pclk_parents =3D { .fw_name =3D= "sysclk" }; + +#define A5_SYS_PCLK(_name, _reg, _bit, _flags) \ + A5_PCLK(_name, _reg, _bit, &a5_sys_pclk_parents, _flags) + +static A5_SYS_PCLK(sys_reset_ctrl, SYS_CLK_EN0_REG0, 1, 0); +static A5_SYS_PCLK(sys_pwr_ctrl, SYS_CLK_EN0_REG0, 3, 0); +static A5_SYS_PCLK(sys_pad_ctrl, SYS_CLK_EN0_REG0, 4, 0); +static A5_SYS_PCLK(sys_ctrl, SYS_CLK_EN0_REG0, 5, 0); +static A5_SYS_PCLK(sys_ts_pll, SYS_CLK_EN0_REG0, 6, 0); + +/* + * NOTE: sys_dev_arb provides the clock to the ETH and SPICC arbiters that + * access the AXI bus. + */ +static A5_SYS_PCLK(sys_dev_arb, SYS_CLK_EN0_REG0, 7, 0); +static A5_SYS_PCLK(sys_mailbox, SYS_CLK_EN0_REG0, 10, 0); +static A5_SYS_PCLK(sys_jtag_ctrl, SYS_CLK_EN0_REG0, 12, 0); +static A5_SYS_PCLK(sys_ir_ctrl, SYS_CLK_EN0_REG0, 13, 0); +static A5_SYS_PCLK(sys_msr_clk, SYS_CLK_EN0_REG0, 15, 0); +static A5_SYS_PCLK(sys_rom, SYS_CLK_EN0_REG0, 16, 0); +static A5_SYS_PCLK(sys_cpu_apb, SYS_CLK_EN0_REG0, 18, 0); +static A5_SYS_PCLK(sys_rsa, SYS_CLK_EN0_REG0, 19, 0); +static A5_SYS_PCLK(sys_saradc, SYS_CLK_EN0_REG0, 20, 0); +static A5_SYS_PCLK(sys_startup, SYS_CLK_EN0_REG0, 21, 0); +static A5_SYS_PCLK(sys_secure, SYS_CLK_EN0_REG0, 22, 0); +static A5_SYS_PCLK(sys_spifc, SYS_CLK_EN0_REG0, 23, 0); +static A5_SYS_PCLK(sys_dspa, SYS_CLK_EN0_REG0, 24, 0); +static A5_SYS_PCLK(sys_nna, SYS_CLK_EN0_REG0, 25, 0); +static A5_SYS_PCLK(sys_eth_mac, SYS_CLK_EN0_REG0, 26, 0); +static A5_SYS_PCLK(sys_rama, SYS_CLK_EN0_REG0, 28, 0); +static A5_SYS_PCLK(sys_ramb, SYS_CLK_EN0_REG0, 30, 0); +static A5_SYS_PCLK(sys_audio_top, SYS_CLK_EN0_REG1, 0, 0); +static A5_SYS_PCLK(sys_audio_vad, SYS_CLK_EN0_REG1, 1, 0); +static A5_SYS_PCLK(sys_usb, SYS_CLK_EN0_REG1, 2, 0); +static A5_SYS_PCLK(sys_sd_emmc_a, SYS_CLK_EN0_REG1, 3, 0); +static A5_SYS_PCLK(sys_sd_emmc_c, SYS_CLK_EN0_REG1, 4, 0); +static A5_SYS_PCLK(sys_pwm_ab, SYS_CLK_EN0_REG1, 5, 0); +static A5_SYS_PCLK(sys_pwm_cd, SYS_CLK_EN0_REG1, 6, 0); +static A5_SYS_PCLK(sys_pwm_ef, SYS_CLK_EN0_REG1, 7, 0); +static A5_SYS_PCLK(sys_pwm_gh, SYS_CLK_EN0_REG1, 8, 0); +static A5_SYS_PCLK(sys_spicc_1, SYS_CLK_EN0_REG1, 9, 0); +static A5_SYS_PCLK(sys_spicc_0, SYS_CLK_EN0_REG1, 10, 0); +static A5_SYS_PCLK(sys_uart_a, SYS_CLK_EN0_REG1, 11, 0); +static A5_SYS_PCLK(sys_uart_b, SYS_CLK_EN0_REG1, 12, 0); +static A5_SYS_PCLK(sys_uart_c, SYS_CLK_EN0_REG1, 13, 0); +static A5_SYS_PCLK(sys_uart_d, SYS_CLK_EN0_REG1, 14, 0); +static A5_SYS_PCLK(sys_uart_e, SYS_CLK_EN0_REG1, 15, 0); +static A5_SYS_PCLK(sys_i2c_m_a, SYS_CLK_EN0_REG1, 16, 0); +static A5_SYS_PCLK(sys_i2c_m_b, SYS_CLK_EN0_REG1, 17, 0); +static A5_SYS_PCLK(sys_i2c_m_c, SYS_CLK_EN0_REG1, 18, 0); +static A5_SYS_PCLK(sys_i2c_m_d, SYS_CLK_EN0_REG1, 19, 0); +static A5_SYS_PCLK(sys_rtc, SYS_CLK_EN0_REG1, 21, 0); + +static const struct clk_parent_data a5_axi_clk_parents =3D { .fw_name =3D = "axiclk" }; + +#define A5_AXI_CLK(_name, _reg, _bit, _flags) \ + A5_PCLK(_name, _reg, _bit, &a5_axi_clk_parents, _flags) + +static A5_AXI_CLK(axi_audio_vad, AXI_CLK_EN0, 0, 0); +static A5_AXI_CLK(axi_audio_top, AXI_CLK_EN0, 1, 0); +static A5_AXI_CLK(axi_ramb, AXI_CLK_EN0, 5, 0); +static A5_AXI_CLK(axi_rama, AXI_CLK_EN0, 6, 0); +static A5_AXI_CLK(axi_nna, AXI_CLK_EN0, 12, 0); + +/* + * NOTE: axi_dev1_dmc provides the clock for the peripherals(EMMC, SDIO, + * sec_top, USB, Audio) to access the AXI bus of the DDR. + */ +static A5_AXI_CLK(axi_dev1_dmc, AXI_CLK_EN0, 13, 0); + +/* + * NOTE: axi_dev0_dmc provides the clock for the peripherals(ETH and SPICC) + * to access the AXI bus of the DDR. + */ +static A5_AXI_CLK(axi_dev0_dmc, AXI_CLK_EN0, 14, 0); +static A5_AXI_CLK(axi_dsp_dmc, AXI_CLK_EN0, 15, 0); + +static struct clk_regmap a5_clk_12_24m_in =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLK12_24_CTRL, + .bit_idx =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "clk_12_24m_in", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_clk_12_24m =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLK12_24_CTRL, + .shift =3D 10, + .width =3D 1, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "clk_12_24m", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_clk_12_24m_in.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_fclk_25m_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLK12_24_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_25m_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fix", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_fclk_25m =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLK12_24_CTRL, + .bit_idx =3D 12, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_25m", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_fclk_25m_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* + * Channel 4 5 8 9 10 11 13 14 15 16 18 are not connected. + * + * gp1 is designed for DSU (DynamIQ Shared Unit) alone. It cannot be chang= ed + * arbitrarily. gp1 is read-only in the kernel and is only open for debug + * purposes. + */ +static u32 a5_gen_parent_table[] =3D { 0, 1, 2, 3, 6, 7, 12, 17, 19, 20, 2= 1, 22, + 23, 24, 25, 26, 27, 28}; + +static const struct clk_parent_data a5_gen_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .hw =3D &a5_rtc_clk.hw }, + { .fw_name =3D "sysplldiv16" }, + { .fw_name =3D "ddr" }, + { .fw_name =3D "gp1" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "clkmsr" }, + { .fw_name =3D "cpudiv16" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "fdiv7" }, + { .fw_name =3D "mpll0" }, + { .fw_name =3D "mpll1" }, + { .fw_name =3D "mpll2" }, + { .fw_name =3D "mpll3" } +}; + +static struct clk_regmap a5_gen_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D GEN_CLK_CTRL, + .mask =3D 0x1f, + .shift =3D 12, + .table =3D a5_gen_parent_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gen_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D a5_gen_parent_data, + .num_parents =3D ARRAY_SIZE(a5_gen_parent_data), + }, +}; + +static struct clk_regmap a5_gen_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D GEN_CLK_CTRL, + .shift =3D 0, + .width =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gen_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_gen_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a5_gen =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D GEN_CLK_CTRL, + .bit_idx =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gen", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_gen_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +#define A5_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \ + MESON_COMP_SEL(a5_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0) + +#define A5_COMP_DIV(_name, _reg, _shift, _width) \ + MESON_COMP_DIV(a5_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT) + +#define A5_COMP_GATE(_name, _reg, _bit) \ + MESON_COMP_GATE(a5_, _name, _reg, _bit, CLK_SET_RATE_PARENT) + +static const struct clk_parent_data a5_saradc_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "sysclk" } +}; + +static A5_COMP_SEL(saradc, SAR_CLK_CTRL0, 9, 0x3, a5_saradc_parent_data); +static A5_COMP_DIV(saradc, SAR_CLK_CTRL0, 0, 8); +static A5_COMP_GATE(saradc, SAR_CLK_CTRL0, 8); + +static const struct clk_parent_data a5_pwm_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .hw =3D &a5_rtc_clk.hw }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv3" } +}; + +static A5_COMP_SEL(pwm_a, PWM_CLK_AB_CTRL, 9, 0x3, a5_pwm_parent_data); +static A5_COMP_DIV(pwm_a, PWM_CLK_AB_CTRL, 0, 8); +static A5_COMP_GATE(pwm_a, PWM_CLK_AB_CTRL, 8); + +static A5_COMP_SEL(pwm_b, PWM_CLK_AB_CTRL, 25, 0x3, a5_pwm_parent_data); +static A5_COMP_DIV(pwm_b, PWM_CLK_AB_CTRL, 16, 8); +static A5_COMP_GATE(pwm_b, PWM_CLK_AB_CTRL, 24); + +static A5_COMP_SEL(pwm_c, PWM_CLK_CD_CTRL, 9, 0x3, a5_pwm_parent_data); +static A5_COMP_DIV(pwm_c, PWM_CLK_CD_CTRL, 0, 8); +static A5_COMP_GATE(pwm_c, PWM_CLK_CD_CTRL, 8); + +static A5_COMP_SEL(pwm_d, PWM_CLK_CD_CTRL, 25, 0x3, a5_pwm_parent_data); +static A5_COMP_DIV(pwm_d, PWM_CLK_CD_CTRL, 16, 8); +static A5_COMP_GATE(pwm_d, PWM_CLK_CD_CTRL, 24); + +static A5_COMP_SEL(pwm_e, PWM_CLK_EF_CTRL, 9, 0x3, a5_pwm_parent_data); +static A5_COMP_DIV(pwm_e, PWM_CLK_EF_CTRL, 0, 8); +static A5_COMP_GATE(pwm_e, PWM_CLK_EF_CTRL, 8); + +static A5_COMP_SEL(pwm_f, PWM_CLK_EF_CTRL, 25, 0x3, a5_pwm_parent_data); +static A5_COMP_DIV(pwm_f, PWM_CLK_EF_CTRL, 16, 8); +static A5_COMP_GATE(pwm_f, PWM_CLK_EF_CTRL, 24); + +static A5_COMP_SEL(pwm_g, PWM_CLK_GH_CTRL, 9, 0x3, a5_pwm_parent_data); +static A5_COMP_DIV(pwm_g, PWM_CLK_GH_CTRL, 0, 8); +static A5_COMP_GATE(pwm_g, PWM_CLK_GH_CTRL, 8); + +static A5_COMP_SEL(pwm_h, PWM_CLK_GH_CTRL, 25, 0x3, a5_pwm_parent_data); +static A5_COMP_DIV(pwm_h, PWM_CLK_GH_CTRL, 16, 8); +static A5_COMP_GATE(pwm_h, PWM_CLK_GH_CTRL, 24); + +/* + * NOTE: Channel 7 is gp1, because gp1 is designed for DSU, so spicc does = not + * support this source in the driver. + */ +static const struct clk_parent_data a5_spicc_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "sysclk" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "fdiv7" } +}; + +static A5_COMP_SEL(spicc_0, SPICC_CLK_CTRL, 7, 0x7, a5_spicc_parent_data); +static A5_COMP_DIV(spicc_0, SPICC_CLK_CTRL, 0, 6); +static A5_COMP_GATE(spicc_0, SPICC_CLK_CTRL, 6); + +static A5_COMP_SEL(spicc_1, SPICC_CLK_CTRL, 23, 0x7, a5_spicc_parent_data); +static A5_COMP_DIV(spicc_1, SPICC_CLK_CTRL, 16, 6); +static A5_COMP_GATE(spicc_1, SPICC_CLK_CTRL, 22); + +static const struct clk_parent_data a5_sd_emmc_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "mpll2" }, + { .fw_name =3D "mpll3" }, + { .fw_name =3D "gp0" } +}; + +static A5_COMP_SEL(sd_emmc_a, SD_EMMC_CLK_CTRL, 9, 0x7, a5_sd_emmc_parent_= data); +static A5_COMP_DIV(sd_emmc_a, SD_EMMC_CLK_CTRL, 0, 7); +static A5_COMP_GATE(sd_emmc_a, SD_EMMC_CLK_CTRL, 7); + +static A5_COMP_SEL(sd_emmc_c, NAND_CLK_CTRL, 9, 0x7, a5_sd_emmc_parent_dat= a); +static A5_COMP_DIV(sd_emmc_c, NAND_CLK_CTRL, 0, 7); +static A5_COMP_GATE(sd_emmc_c, NAND_CLK_CTRL, 7); + +static struct clk_regmap a5_ts_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D TS_CLK_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "ts_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "oscin", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_ts =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D TS_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "ts", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_ts_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor a5_eth_125m_div =3D { + .mult =3D 1, + .div =3D 8, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_125m_div", + .ops =3D &clk_fixed_factor_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fdiv2", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_eth_125m =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ETH_CLK_CTRL, + .bit_idx =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_125m", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_eth_125m_div.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_eth_rmii_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ETH_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_rmii_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fdiv2", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_eth_rmii =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ETH_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_rmii", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_eth_rmii_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* Channel 6 is gp1. */ +static u32 a5_dspa_parent_table[] =3D { 0, 1, 2, 3, 4, 5, 7}; + +static const struct clk_parent_data a5_dspa_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "rtc" }, /* rtc_pll */ + { .fw_name =3D "hifi" }, + { .fw_name =3D "fdiv4" }, + { .hw =3D &a5_rtc_clk.hw } +}; + +static struct clk_regmap a5_dspa_0_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D DSPA_CLK_CTRL0, + .mask =3D 0x7, + .shift =3D 10, + .table =3D a5_dspa_parent_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_0_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D a5_dspa_parent_data, + .num_parents =3D ARRAY_SIZE(a5_dspa_parent_data), + }, +}; + +static struct clk_regmap a5_dspa_0_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D DSPA_CLK_CTRL0, + .shift =3D 0, + .width =3D 10, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_0_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_dspa_0_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a5_dspa_0 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D DSPA_CLK_CTRL0, + .bit_idx =3D 13, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_0", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_dspa_0_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a5_dspa_1_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D DSPA_CLK_CTRL0, + .mask =3D 0x7, + .shift =3D 26, + .table =3D a5_dspa_parent_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_1_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D a5_dspa_parent_data, + .num_parents =3D ARRAY_SIZE(a5_dspa_parent_data), + }, +}; + +static struct clk_regmap a5_dspa_1_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D DSPA_CLK_CTRL0, + .shift =3D 16, + .width =3D 10, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_1_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_dspa_1_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a5_dspa_1 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D DSPA_CLK_CTRL0, + .bit_idx =3D 29, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_1", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_dspa_1_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a5_dspa =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D DSPA_CLK_CTRL0, + .mask =3D 0x1, + .shift =3D 15, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_dspa_0.hw, + &a5_dspa_1.hw + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +#define A5_COMP_SEL_WITH_TAB(_name, _reg, _shift, _mask, _pdata, _table) \ + MESON_COMP_SEL(a5_, _name, _reg, _shift, _mask, _pdata, _table, 0, 0) + +/* Channel 6 is gp1. */ +static u32 a5_nna_parent_table[] =3D { 0, 1, 2, 3, 4, 5, 7}; + +static const struct clk_parent_data a5_nna_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "hifi" } +}; + +static A5_COMP_SEL_WITH_TAB(nna_core, NNA_CLK_CNTL, 9, 0x7, + a5_nna_parent_data, a5_nna_parent_table); +static A5_COMP_DIV(nna_core, NNA_CLK_CNTL, 0, 7); +static A5_COMP_GATE(nna_core, NNA_CLK_CNTL, 8); + +static A5_COMP_SEL_WITH_TAB(nna_axi, NNA_CLK_CNTL, 25, 0x7, + a5_nna_parent_data, a5_nna_parent_table); +static A5_COMP_DIV(nna_axi, NNA_CLK_CNTL, 16, 7); +static A5_COMP_GATE(nna_axi, NNA_CLK_CNTL, 24); + +static struct clk_hw *a5_peripherals_hw_clks[] =3D { + [CLKID_RTC_DUALDIV_CLKIN] =3D &a5_rtc_dualdiv_clkin.hw, + [CLKID_RTC_DUALDIV] =3D &a5_rtc_dualdiv.hw, + [CLKID_RTC_DUALDIV_SEL] =3D &a5_rtc_dualdiv_sel.hw, + [CLKID_RTC_DUALDIV_CLKOUT] =3D &a5_rtc_dualdiv_clkout.hw, + [CLKID_RTC_CLK] =3D &a5_rtc_clk.hw, + [CLKID_SYS_RESET_CTRL] =3D &a5_sys_reset_ctrl.hw, + [CLKID_SYS_PWR_CTRL] =3D &a5_sys_pwr_ctrl.hw, + [CLKID_SYS_PAD_CTRL] =3D &a5_sys_pad_ctrl.hw, + [CLKID_SYS_CTRL] =3D &a5_sys_ctrl.hw, + [CLKID_SYS_TS_PLL] =3D &a5_sys_ts_pll.hw, + [CLKID_SYS_DEV_ARB] =3D &a5_sys_dev_arb.hw, + [CLKID_SYS_MAILBOX] =3D &a5_sys_mailbox.hw, + [CLKID_SYS_JTAG_CTRL] =3D &a5_sys_jtag_ctrl.hw, + [CLKID_SYS_IR_CTRL] =3D &a5_sys_ir_ctrl.hw, + [CLKID_SYS_MSR_CLK] =3D &a5_sys_msr_clk.hw, + [CLKID_SYS_ROM] =3D &a5_sys_rom.hw, + [CLKID_SYS_CPU_ARB] =3D &a5_sys_cpu_apb.hw, + [CLKID_SYS_RSA] =3D &a5_sys_rsa.hw, + [CLKID_SYS_SARADC] =3D &a5_sys_saradc.hw, + [CLKID_SYS_STARTUP] =3D &a5_sys_startup.hw, + [CLKID_SYS_SECURE] =3D &a5_sys_secure.hw, + [CLKID_SYS_SPIFC] =3D &a5_sys_spifc.hw, + [CLKID_SYS_DSPA] =3D &a5_sys_dspa.hw, + [CLKID_SYS_NNA] =3D &a5_sys_nna.hw, + [CLKID_SYS_ETH_MAC] =3D &a5_sys_eth_mac.hw, + [CLKID_SYS_RAMA] =3D &a5_sys_rama.hw, + [CLKID_SYS_RAMB] =3D &a5_sys_ramb.hw, + [CLKID_SYS_AUDIO_TOP] =3D &a5_sys_audio_top.hw, + [CLKID_SYS_AUDIO_VAD] =3D &a5_sys_audio_vad.hw, + [CLKID_SYS_USB] =3D &a5_sys_usb.hw, + [CLKID_SYS_SD_EMMC_A] =3D &a5_sys_sd_emmc_a.hw, + [CLKID_SYS_SD_EMMC_C] =3D &a5_sys_sd_emmc_c.hw, + [CLKID_SYS_PWM_AB] =3D &a5_sys_pwm_ab.hw, + [CLKID_SYS_PWM_CD] =3D &a5_sys_pwm_cd.hw, + [CLKID_SYS_PWM_EF] =3D &a5_sys_pwm_ef.hw, + [CLKID_SYS_PWM_GH] =3D &a5_sys_pwm_gh.hw, + [CLKID_SYS_SPICC_1] =3D &a5_sys_spicc_1.hw, + [CLKID_SYS_SPICC_0] =3D &a5_sys_spicc_0.hw, + [CLKID_SYS_UART_A] =3D &a5_sys_uart_a.hw, + [CLKID_SYS_UART_B] =3D &a5_sys_uart_b.hw, + [CLKID_SYS_UART_C] =3D &a5_sys_uart_c.hw, + [CLKID_SYS_UART_D] =3D &a5_sys_uart_d.hw, + [CLKID_SYS_UART_E] =3D &a5_sys_uart_e.hw, + [CLKID_SYS_I2C_M_A] =3D &a5_sys_i2c_m_a.hw, + [CLKID_SYS_I2C_M_B] =3D &a5_sys_i2c_m_b.hw, + [CLKID_SYS_I2C_M_C] =3D &a5_sys_i2c_m_c.hw, + [CLKID_SYS_I2C_M_D] =3D &a5_sys_i2c_m_d.hw, + [CLKID_SYS_RTC] =3D &a5_sys_rtc.hw, + [CLKID_AXI_AUDIO_VAD] =3D &a5_axi_audio_vad.hw, + [CLKID_AXI_AUDIO_TOP] =3D &a5_axi_audio_top.hw, + [CLKID_AXI_RAMB] =3D &a5_axi_ramb.hw, + [CLKID_AXI_RAMA] =3D &a5_axi_rama.hw, + [CLKID_AXI_NNA] =3D &a5_axi_nna.hw, + [CLKID_AXI_DEV1_DMC] =3D &a5_axi_dev1_dmc.hw, + [CLKID_AXI_DEV0_DMC] =3D &a5_axi_dev0_dmc.hw, + [CLKID_AXI_DSP_DMC] =3D &a5_axi_dsp_dmc.hw, + [CLKID_12_24M_IN] =3D &a5_clk_12_24m_in.hw, + [CLKID_12M_24M] =3D &a5_clk_12_24m.hw, + [CLKID_FCLK_25M_DIV] =3D &a5_fclk_25m_div.hw, + [CLKID_FCLK_25M] =3D &a5_fclk_25m.hw, + [CLKID_GEN_SEL] =3D &a5_gen_sel.hw, + [CLKID_GEN_DIV] =3D &a5_gen_div.hw, + [CLKID_GEN] =3D &a5_gen.hw, + [CLKID_SARADC_SEL] =3D &a5_saradc_sel.hw, + [CLKID_SARADC_DIV] =3D &a5_saradc_div.hw, + [CLKID_SARADC] =3D &a5_saradc.hw, + [CLKID_PWM_A_SEL] =3D &a5_pwm_a_sel.hw, + [CLKID_PWM_A_DIV] =3D &a5_pwm_a_div.hw, + [CLKID_PWM_A] =3D &a5_pwm_a.hw, + [CLKID_PWM_B_SEL] =3D &a5_pwm_b_sel.hw, + [CLKID_PWM_B_DIV] =3D &a5_pwm_b_div.hw, + [CLKID_PWM_B] =3D &a5_pwm_b.hw, + [CLKID_PWM_C_SEL] =3D &a5_pwm_c_sel.hw, + [CLKID_PWM_C_DIV] =3D &a5_pwm_c_div.hw, + [CLKID_PWM_C] =3D &a5_pwm_c.hw, + [CLKID_PWM_D_SEL] =3D &a5_pwm_d_sel.hw, + [CLKID_PWM_D_DIV] =3D &a5_pwm_d_div.hw, + [CLKID_PWM_D] =3D &a5_pwm_d.hw, + [CLKID_PWM_E_SEL] =3D &a5_pwm_e_sel.hw, + [CLKID_PWM_E_DIV] =3D &a5_pwm_e_div.hw, + [CLKID_PWM_E] =3D &a5_pwm_e.hw, + [CLKID_PWM_F_SEL] =3D &a5_pwm_f_sel.hw, + [CLKID_PWM_F_DIV] =3D &a5_pwm_f_div.hw, + [CLKID_PWM_F] =3D &a5_pwm_f.hw, + [CLKID_PWM_G_SEL] =3D &a5_pwm_g_sel.hw, + [CLKID_PWM_G_DIV] =3D &a5_pwm_g_div.hw, + [CLKID_PWM_G] =3D &a5_pwm_g.hw, + [CLKID_PWM_H_SEL] =3D &a5_pwm_h_sel.hw, + [CLKID_PWM_H_DIV] =3D &a5_pwm_h_div.hw, + [CLKID_PWM_H] =3D &a5_pwm_h.hw, + [CLKID_SPICC_0_SEL] =3D &a5_spicc_0_sel.hw, + [CLKID_SPICC_0_DIV] =3D &a5_spicc_0_div.hw, + [CLKID_SPICC_0] =3D &a5_spicc_0.hw, + [CLKID_SPICC_1_SEL] =3D &a5_spicc_1_sel.hw, + [CLKID_SPICC_1_DIV] =3D &a5_spicc_1_div.hw, + [CLKID_SPICC_1] =3D &a5_spicc_1.hw, + [CLKID_SD_EMMC_A_SEL] =3D &a5_sd_emmc_a_sel.hw, + [CLKID_SD_EMMC_A_DIV] =3D &a5_sd_emmc_a_div.hw, + [CLKID_SD_EMMC_A] =3D &a5_sd_emmc_a.hw, + [CLKID_SD_EMMC_C_SEL] =3D &a5_sd_emmc_c_sel.hw, + [CLKID_SD_EMMC_C_DIV] =3D &a5_sd_emmc_c_div.hw, + [CLKID_SD_EMMC_C] =3D &a5_sd_emmc_c.hw, + [CLKID_TS_DIV] =3D &a5_ts_div.hw, + [CLKID_TS] =3D &a5_ts.hw, + [CLKID_ETH_125M_DIV] =3D &a5_eth_125m_div.hw, + [CLKID_ETH_125M] =3D &a5_eth_125m.hw, + [CLKID_ETH_RMII_DIV] =3D &a5_eth_rmii_div.hw, + [CLKID_ETH_RMII] =3D &a5_eth_rmii.hw, + [CLKID_DSPA_0_SEL] =3D &a5_dspa_0_sel.hw, + [CLKID_DSPA_0_DIV] =3D &a5_dspa_0_div.hw, + [CLKID_DSPA_0] =3D &a5_dspa_0.hw, + [CLKID_DSPA_1_SEL] =3D &a5_dspa_1_sel.hw, + [CLKID_DSPA_1_DIV] =3D &a5_dspa_1_div.hw, + [CLKID_DSPA_1] =3D &a5_dspa_1.hw, + [CLKID_DSPA] =3D &a5_dspa.hw, + [CLKID_NNA_CORE_SEL] =3D &a5_nna_core_sel.hw, + [CLKID_NNA_CORE_DIV] =3D &a5_nna_core_div.hw, + [CLKID_NNA_CORE] =3D &a5_nna_core.hw, + [CLKID_NNA_AXI_SEL] =3D &a5_nna_axi_sel.hw, + [CLKID_NNA_AXI_DIV] =3D &a5_nna_axi_div.hw, + [CLKID_NNA_AXI] =3D &a5_nna_axi.hw, +}; + +static const struct meson_clkc_data a5_peripherals_clkc_data =3D { + .hw_clks =3D { + .hws =3D a5_peripherals_hw_clks, + .num =3D ARRAY_SIZE(a5_peripherals_hw_clks), + }, +}; + +static const struct of_device_id a5_peripherals_clkc_match_table[] =3D { + { + .compatible =3D "amlogic,a5-peripherals-clkc", + .data =3D &a5_peripherals_clkc_data, + }, + {} +}; +MODULE_DEVICE_TABLE(of, a5_peripherals_clkc_match_table); + +static struct platform_driver a5_peripherals_clkc_driver =3D { + .probe =3D meson_clkc_mmio_probe, + .driver =3D { + .name =3D "a5-peripherals-clkc", + .of_match_table =3D a5_peripherals_clkc_match_table, + }, +}; +module_platform_driver(a5_peripherals_clkc_driver); + +MODULE_DESCRIPTION("Amlogic A5 Peripherals Clock Controller driver"); +MODULE_AUTHOR("Chuan Liu "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("CLK_MESON"); --=20 2.42.0 From nobody Wed Dec 17 14:13:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 98ED52F7AD5; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; cv=none; b=uM6YjbZA/lSV11bTES9fALPEN1GmhyOoPJ8uxt2N813X/WwRkDreqAQqaWcD5BjBssRYQQgeOzSmGhN2gQFYVs/+0R320YpDnqGdMxqq3mdQj266GreVLMEllJHegalVlEy5l6+QB2wb/9z1Lni7vg8/BTEpFxWhixf+qacsuow= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; c=relaxed/simple; bh=usjXaJmrQBaOByOo0f9SIIGQaMPOLSk+orCRo+WCesE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Tifc3eS+8uRvXqKOXUKmX9L9bYRxFTDlTIW8lx+IL6/CdJTwxZv45nfyZXu1rgNo1rZDjOKYN22Ut89Aj9gJWCePkQbqi1vLWiDRlPJZFCL3DEAELZ760D9oDaw/WvS/GQdKnayRfFU9WeXxgW7leRQfxD1cGXJpOkDEV1vQsuA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pnLj+8cs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pnLj+8cs" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6363EC19422; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225052; bh=usjXaJmrQBaOByOo0f9SIIGQaMPOLSk+orCRo+WCesE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=pnLj+8csA698jLcbD0B62hmLfVWZ4vv3brRxWO4isPsHPWOcZ2AWBUlo3EhMxxOZ0 Ex3/ZulkIXvT6lvqK2xyE2xAhkysfhbM18VXzg4YpRPISpTYk9dMA53pZyZTB4Ncx4 5pNu/028/eLOz9blzV1xcdsVEzvr8FH3/vAIWKtGJ6DUvhunwVh6WLDUKWttiu43Vc IJwXqAKFm1rUoC0I5NZH9e16Bhu34+YdejLGeVgkXOSC7EAPo+drnfM1T+ZttWu+Cq dHdm1POQjPMHjJ7JS0cqAVMQLNp7A2qfhIBrXWVs3FoPpyqi7pnRuhDSTpSwvZ8RMk y2pP3hh3yPilw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57E52CCA471; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:30 +0800 Subject: [PATCH 17/19] arm64: dts: amlogic: A5: Add scmi-clk node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-a4_a5_add_clock_driver-v1-17-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=1185; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=ZspyBFWCUNiYBTdpBZ0EtAZp2GBczlcrxn+GjTrWL+k=; b=rG9NwK2T9qExtErn9VwTiBIYDzzQzUyyccAHrFcR2+2hwFvuiVrDYBIPujs3LrMfmhVAgVpdO 9UaELmKxZU+BaxZOjeihIsDoZmQ6xX37P+MfarjJmq/cEuk+PFVP0LU X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add scmi-clk device node information for the Amlogic A5 SoC family. Signed-off-by: Chuan Liu --- arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 29 +++++++++++++++++++++++++= ++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-a5.dtsi index b1da8cbaa25a..3b0e70211268 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi @@ -48,6 +48,35 @@ pwrc: power-controller { #power-domain-cells =3D <1>; }; }; + + sram0: sram@f702a000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0xf702a000 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x0 0xf702a000 0x100>; + + scmi_buf0: scmi-sram-section@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x100>; + }; + }; + + firmware { + scmi { + compatible =3D "arm,scmi-smc"; + arm,smc-id =3D <0x820000C1>; + shmem =3D <&scmi_buf0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_clk: protocol@14 { + reg =3D <0x14>; + #clock-cells =3D <1>; + }; + }; + }; + }; =20 &apb { --=20 2.42.0 From nobody Wed Dec 17 14:13:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4F442F7AD8; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; cv=none; b=pLNK0D6nTtDfmT5QgwUs63rjfxSlA4R3yxD+Lp60gb0Yq5tfNQaHktXh5tvLPx7m6yeWN2LyfUyNPYrAoxK1Xm7JlE7nr4eWJFqyCkRvzQxmom0Vz8EwgpUrAfRgHITVTrTTyBFZ1NlqLvaibxbh3oz/PIl+0E9zQtxX24vK7SM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; c=relaxed/simple; bh=iErMSw2Lyr6Fmu4FymWLOW0ESDvPsMZJihkoB1lmfRI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fPfpxRisyqFOueblfFS1BbLH0urbDW1VeKR1KQevxS3wobsotCFZ6uE6CxiO/W5NbkTHV89gBc3TDgc2m7frNmPFGHk8tM272Z7VjBNdVA5cV1w1DhsVW2ZyK1Tp0kbGAFaFww4/Vjl+XlTXQLrxEinol7U5yHYRSMTKgsIEHc8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BuZWZ6pf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BuZWZ6pf" Received: by smtp.kernel.org (Postfix) with ESMTPS id 74BAEC2BC87; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225052; bh=iErMSw2Lyr6Fmu4FymWLOW0ESDvPsMZJihkoB1lmfRI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=BuZWZ6pfCnTh8LtgpYTG/NTL1OPECQihA9IPACJdP5aLvsywy2AgjVyGmOBBURfAj lWtBy/5Oej8axI29aJx4pabWX9S8Pk2PJVylhe+x7CbTfZT5tRnEKLZ1pt0MPVmAFi nzTQzx45pTc87A5bT0YdByoVeFu01p6X2uRpdp7+BK3f4ulrvX3oywrxki75Ym8cvJ ycd6jLhqG8fOaIE1MTNUE3H3sFhRxmaHKbaqGU9eZQE/86yMJunslBdM0ALSHgKYWB OnaZPeXoQsjmx8T/WYnzXXb1sM96rDChkDDa/9SvwpGaLtOomkvQ1StFWuE5Zd0WxP /KYygW21CgYqw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6846FCCA472; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:31 +0800 Subject: [PATCH 18/19] arm64: dts: amlogic: A5: Add PLL controller node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-a4_a5_add_clock_driver-v1-18-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=1206; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=bQhUJaPTXEFMSauXPfNU5Yja/N+Lz2eh2uhawupxhwk=; b=UElGDgkVJLajjfM34iPcghGIOuiB/lpPmFynnVW+ce/mdO2+P10mxC4rS0P1YJUZZCzFnWhYo QuYSVMIy9gBBKgc+CYr1bPud4fDnT8BSZMaIRW0C8s7CRGcba/vkzwx X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add PLL controller node for A5 SoC family. Signed-off-by: Chuan Liu --- arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-a5.dtsi index 3b0e70211268..89f7b5ff4ea3 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi @@ -6,6 +6,9 @@ #include "amlogic-a4-common.dtsi" #include "amlogic-a5-reset.h" #include +#include +#include + / { cpus { #address-cells =3D <2>; @@ -96,4 +99,16 @@ gpio_intc: interrupt-controller@4080 { amlogic,channel-interrupts =3D <10 11 12 13 14 15 16 17 18 19 20 21>; }; + + clkc_pll: clock-controller@8000 { + compatible =3D "amlogic,a5-pll-clkc"; + reg =3D <0x0 0x8000 0x0 0x1a4>; + #clock-cells =3D <1>; + clocks =3D <&xtal>, + <&scmi_clk CLKID_FIXED_PLL_DCO>, + <&scmi_clk CLKID_FIXED_PLL>; + clock-names =3D "xtal", + "fix_dco", + "fix"; + }; }; --=20 2.42.0 From nobody Wed Dec 17 14:13:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE4222F83C3; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; cv=none; b=UjY+Dyj3zCwdMOPMjV2dNfoPXhTjW9jk4tJjol5Yo9m4K5Dk6ENok+DrxmS/jZ3RFmPqIpAZ3hC5Kgy0e4xXMOq+hqmIg4Bheg22V7CwmGTZwZZP2W0IbPAvvdl+n3N+ujvnBFlNbOu7hyy7UweIUTK85ORo2ab9gCjifH+rljk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; c=relaxed/simple; bh=GhazWRbsOSZcBLYhB/FQbhXm3/61sthie18NPBjHd0g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RjnNhrcoFqqImH50TmR9zFR0+bmIhlmP0rRHduXKyADif0xKTmvaCEtoTcghORUfUQrc5vh3pnNh6xkKHzH0cEdRidtPtuYqm53MJ5achaEEaJDBkK9BnXisRILpsphXlBBZIkTxOqJ7DGITM6tFrx567QHhgsykWA/VabcSs2Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qCpPidns; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qCpPidns" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8DB8DC2BCB0; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225052; bh=GhazWRbsOSZcBLYhB/FQbhXm3/61sthie18NPBjHd0g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=qCpPidns8gn/ylXUskUqdeKTTDpZdsjVzfg7KuSY9msPWwcCeN+Sh3AW4TrNPv1eq Thr4/au1PgLNQsHbtQyOKfz7fBFdu2DUagoip9SYKa7i9KBuuPIKx51Myf4x0qYQKG k8IgUM2rO+vfaau406VBs2hRUfNHsEzf1AGjrm8P5nh4ukeTbgBZUkuC7NLyTLOtVY qm3yHwzjobe4BJCg9WjJhDqCVW7Sloqr+fpL7DTRZ/QUw5QtOYxrCuH4Tz/cBFHi4X 03XgM5t0Wk+2FtPonQf/8mt8BI48yHRr2ahyP6MlnbcTXIJdd2Y8Hm/XBZMrkOQJt0 DPGLi+dRznQRQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75BE4CCA470; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:32 +0800 Subject: [PATCH 19/19] arm64: dts: amlogic: A5: Add peripheral clock controller node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-a4_a5_add_clock_driver-v1-19-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=2041; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=819hwcypvLPkK6zGwB1cqKbMQOi/dUvVkIknKgOKBPA=; b=Yxou6e6o7eYaQX7ea8PxyQS46pJ+jtcK7m1onlU0UwXsX3ttMyz3/Ts2jBPl6HRVxH7dcdASr d+p/EnVQbr/DBmqr7SkjrupsjApzN85QilFbyXdufDKtY5IGcEaCJDv X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add peripheral clock controller node for A5 SoC family. Signed-off-by: Chuan Liu --- arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 43 +++++++++++++++++++++++++= ++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-a5.dtsi index 89f7b5ff4ea3..406cd52a6474 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include =20 / { cpus { @@ -83,6 +84,48 @@ scmi_clk: protocol@14 { }; =20 &apb { + clkc_periphs: clock-controller@0 { + compatible =3D "amlogic,a5-peripherals-clkc"; + reg =3D <0x0 0x0 0x0 0x224>; + #clock-cells =3D <1>; + clocks =3D <&xtal>, + <&scmi_clk CLKID_OSC>, + <&scmi_clk CLKID_FIXED_PLL>, + <&scmi_clk CLKID_FCLK_DIV2>, + <&scmi_clk CLKID_FCLK_DIV2P5>, + <&scmi_clk CLKID_FCLK_DIV3>, + <&scmi_clk CLKID_FCLK_DIV4>, + <&scmi_clk CLKID_FCLK_DIV5>, + <&scmi_clk CLKID_FCLK_DIV7>, + <&clkc_pll CLKID_MPLL2>, + <&clkc_pll CLKID_MPLL3>, + <&clkc_pll CLKID_GP0_PLL>, + <&scmi_clk CLKID_GP1_PLL>, + <&clkc_pll CLKID_HIFI_PLL>, + <&scmi_clk CLKID_SYS_CLK>, + <&scmi_clk CLKID_AXI_CLK>, + <&scmi_clk CLKID_SYS_PLL_DIV16>, + <&scmi_clk CLKID_CPU_CLK_DIV16>; + clock-names =3D "xtal", + "oscin", + "fix", + "fdiv2", + "fdiv2p5", + "fdiv3", + "fdiv4", + "fdiv5", + "fdiv7", + "mpll2", + "mpll3", + "gp0", + "gp1", + "hifi", + "sysclk", + "axiclk", + "sysplldiv16", + "cpudiv16"; + }; + reset: reset-controller@2000 { compatible =3D "amlogic,a5-reset", "amlogic,meson-s4-reset"; --=20 2.42.0