To pick up the changes in this cset:

commit 2f8f173413f1 ("x86/vmscape: Add conditional IBPB mitigation")
commit a508cec6e521 ("x86/vmscape: Enumerate VMSCAPE bug")
commit c8c2647e69be ("arm64: Make  _midr_in_range_list() an exported function")
commit e3121298c7fc ("arm64: Modify _midr_range() functions to read MIDR/REVIDR internally")

This addresses these perf build warnings:
tools/perf$ ./check-headers.sh
Warning: Kernel ABI header differences:
  diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures
  diff -u tools/arch/arm64/include/asm/cputype.h arch/arm64/include/asm/cputype.h

Please see tools/include/uapi/README for further details.

Signed-off-by: Shivank Garg <shivankg@amd.com>
---
 tools/arch/arm64/include/asm/cputype.h   | 36 ++++++++----------------
 tools/arch/x86/include/asm/cpufeatures.h |  2 ++
 2 files changed, 13 insertions(+), 25 deletions(-)

diff --git a/tools/arch/arm64/include/asm/cputype.h b/tools/arch/arm64/include/asm/cputype.h
index 139d5e87dc95..661735616787 100644
--- a/tools/arch/arm64/include/asm/cputype.h
+++ b/tools/arch/arm64/include/asm/cputype.h
@@ -251,6 +251,16 @@
 
 #define read_cpuid(reg)			read_sysreg_s(SYS_ ## reg)
 
+/*
+ * The CPU ID never changes at run time, so we might as well tell the
+ * compiler that it's constant.  Use this function to read the CPU ID
+ * rather than directly reading processor_id or read_cpuid() directly.
+ */
+static inline u32 __attribute_const__ read_cpuid_id(void)
+{
+	return read_cpuid(MIDR_EL1);
+}
+
 /*
  * Represent a range of MIDR values for a given CPU model and a
  * range of variant/revision values.
@@ -286,31 +296,6 @@ static inline bool midr_is_cpu_model_range(u32 midr, u32 model, u32 rv_min,
 	return _model == model && rv >= rv_min && rv <= rv_max;
 }
 
-static inline bool is_midr_in_range(u32 midr, struct midr_range const *range)
-{
-	return midr_is_cpu_model_range(midr, range->model,
-				       range->rv_min, range->rv_max);
-}
-
-static inline bool
-is_midr_in_range_list(u32 midr, struct midr_range const *ranges)
-{
-	while (ranges->model)
-		if (is_midr_in_range(midr, ranges++))
-			return true;
-	return false;
-}
-
-/*
- * The CPU ID never changes at run time, so we might as well tell the
- * compiler that it's constant.  Use this function to read the CPU ID
- * rather than directly reading processor_id or read_cpuid() directly.
- */
-static inline u32 __attribute_const__ read_cpuid_id(void)
-{
-	return read_cpuid(MIDR_EL1);
-}
-
 struct target_impl_cpu {
 	u64 midr;
 	u64 revidr;
@@ -318,6 +303,7 @@ struct target_impl_cpu {
 };
 
 bool cpu_errata_set_target_impl(u64 num, void *impl_cpus);
+bool is_midr_in_range_list(struct midr_range const *ranges);
 
 static inline u64 __attribute_const__ read_cpuid_mpidr(void)
 {
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index 06fc0479a23f..751ca35386b0 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -495,6 +495,7 @@
 #define X86_FEATURE_TSA_SQ_NO		(21*32+11) /* AMD CPU not vulnerable to TSA-SQ */
 #define X86_FEATURE_TSA_L1_NO		(21*32+12) /* AMD CPU not vulnerable to TSA-L1 */
 #define X86_FEATURE_CLEAR_CPU_BUF_VM	(21*32+13) /* Clear CPU buffers using VERW before VMRUN */
+#define X86_FEATURE_IBPB_EXIT_TO_USER	(21*32+14) /* Use IBPB on exit-to-userspace, see VMSCAPE bug */
 
 /*
  * BUG word(s)
@@ -551,4 +552,5 @@
 #define X86_BUG_ITS			X86_BUG( 1*32+ 7) /* "its" CPU is affected by Indirect Target Selection */
 #define X86_BUG_ITS_NATIVE_ONLY		X86_BUG( 1*32+ 8) /* "its_native_only" CPU is affected by ITS, VMX is not affected */
 #define X86_BUG_TSA			X86_BUG( 1*32+ 9) /* "tsa" CPU is affected by Transient Scheduler Attacks */
+#define X86_BUG_VMSCAPE			X86_BUG( 1*32+10) /* "vmscape" CPU is affected by VMSCAPE attacks from guests */
 #endif /* _ASM_X86_CPUFEATURES_H */
-- 
2.43.0

Hi Shivank,

[ + James, perf-user ML ]

On Mon, Sep 29, 2025 at 06:16:45AM +0000, Shivank Garg wrote:
> To pick up the changes in this cset:
> 
> commit 2f8f173413f1 ("x86/vmscape: Add conditional IBPB mitigation")
> commit a508cec6e521 ("x86/vmscape: Enumerate VMSCAPE bug")
> commit c8c2647e69be ("arm64: Make  _midr_in_range_list() an exported function")
> commit e3121298c7fc ("arm64: Modify _midr_range() functions to read MIDR/REVIDR internally")
> 
> This addresses these perf build warnings:
> tools/perf$ ./check-headers.sh
> Warning: Kernel ABI header differences:
>   diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures
>   diff -u tools/arch/arm64/include/asm/cputype.h arch/arm64/include/asm/cputype.h

Please drop arm64 related syncing, otherwise, it will break perf
building.

At the meantime, James is working on refactoring cpu type definitions
for Arm64, we expect to avoid syncing cputype.h.

Thanks,
Leo

On 9/29/2025 1:57 PM, Leo Yan wrote:
> Hi Shivank,
> 
> [ + James, perf-user ML ]
> 
> On Mon, Sep 29, 2025 at 06:16:45AM +0000, Shivank Garg wrote:
>> To pick up the changes in this cset:
>>
>> commit 2f8f173413f1 ("x86/vmscape: Add conditional IBPB mitigation")
>> commit a508cec6e521 ("x86/vmscape: Enumerate VMSCAPE bug")
>> commit c8c2647e69be ("arm64: Make  _midr_in_range_list() an exported function")
>> commit e3121298c7fc ("arm64: Modify _midr_range() functions to read MIDR/REVIDR internally")
>>
>> This addresses these perf build warnings:
>> tools/perf$ ./check-headers.sh
>> Warning: Kernel ABI header differences:
>>   diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures
>>   diff -u tools/arch/arm64/include/asm/cputype.h arch/arm64/include/asm/cputype.h
> 
> Please drop arm64 related syncing, otherwise, it will break perf
> building.

Sure, I'll send V2 without arm64 sync.

Thanks,
Shivank
> 
> At the meantime, James is working on refactoring cpu type definitions
> for Arm64, we expect to avoid syncing cputype.h.
> 
> Thanks,
> Leo

On 9/29/2025 2:47 PM, Garg, Shivank wrote:
> 
> 
> On 9/29/2025 1:57 PM, Leo Yan wrote:
>> Hi Shivank,
>>
>> [ + James, perf-user ML ]
>>
>> On Mon, Sep 29, 2025 at 06:16:45AM +0000, Shivank Garg wrote:
>>> To pick up the changes in this cset:
>>>
>>> commit 2f8f173413f1 ("x86/vmscape: Add conditional IBPB mitigation")
>>> commit a508cec6e521 ("x86/vmscape: Enumerate VMSCAPE bug")
>>> commit c8c2647e69be ("arm64: Make  _midr_in_range_list() an exported function")
>>> commit e3121298c7fc ("arm64: Modify _midr_range() functions to read MIDR/REVIDR internally")
>>>
>>> This addresses these perf build warnings:
>>> tools/perf$ ./check-headers.sh
>>> Warning: Kernel ABI header differences:
>>>   diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures
>>>   diff -u tools/arch/arm64/include/asm/cputype.h arch/arm64/include/asm/cputype.h
>>
>> Please drop arm64 related syncing, otherwise, it will break perf
>> building.
> 
> Sure, I'll send V2 without arm64 sync.
> 
> Thanks,
> Shivank
>>
>> At the meantime, James is working on refactoring cpu type definitions
>> for Arm64, we expect to avoid syncing cputype.h.
>>
>> Thanks,
>> Leo
> 

tools/perf$ make
  BUILD:   Doing 'make -j128' parallel build
Warning: Kernel ABI header differences:
  diff -u tools/include/linux/cfi_types.h include/linux/cfi_types.h
  diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h
  diff -u tools/include/asm-generic/bitops/__fls.h include/asm-generic/bitops/__fls.h
  diff -u tools/include/asm-generic/bitops/fls.h include/asm-generic/bitops/fls.h
  diff -u tools/include/asm-generic/bitops/fls64.h include/asm-generic/bitops/fls64.h
  diff -u tools/arch/arm64/include/asm/cputype.h arch/arm64/include/asm/cputype.h
  diff -u tools/perf/trace/beauty/include/uapi/linux/fcntl.h include/uapi/linux/fcntl.h
  diff -u tools/perf/trace/beauty/include/uapi/linux/fs.h include/uapi/linux/fs.h

There are a lot of new ABI differences today, so I think it’s best to sync after the merge window?

Thanks,
Shivank