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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2025 06:18:21.0130 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 738df136-4b21-433a-aff0-08ddff1ffd13 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002316.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPFEB07C8E34 To pick up the changes in this cset: commit 2f8f173413f1 ("x86/vmscape: Add conditional IBPB mitigation") commit a508cec6e521 ("x86/vmscape: Enumerate VMSCAPE bug") commit c8c2647e69be ("arm64: Make =C2=A0_midr_in_range_list() an exported f= unction") commit e3121298c7fc ("arm64: Modify _midr_range() functions to read MIDR/RE= VIDR internally") This addresses these perf build warnings: tools/perf$ ./check-headers.sh Warning: Kernel ABI header differences: diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpu= features diff -u tools/arch/arm64/include/asm/cputype.h arch/arm64/include/asm/cpu= type.h Please see tools/include/uapi/README for further details. Signed-off-by: Shivank Garg --- tools/arch/arm64/include/asm/cputype.h | 36 ++++++++---------------- tools/arch/x86/include/asm/cpufeatures.h | 2 ++ 2 files changed, 13 insertions(+), 25 deletions(-) diff --git a/tools/arch/arm64/include/asm/cputype.h b/tools/arch/arm64/incl= ude/asm/cputype.h index 139d5e87dc95..661735616787 100644 --- a/tools/arch/arm64/include/asm/cputype.h +++ b/tools/arch/arm64/include/asm/cputype.h @@ -251,6 +251,16 @@ =20 #define read_cpuid(reg) read_sysreg_s(SYS_ ## reg) =20 +/* + * The CPU ID never changes at run time, so we might as well tell the + * compiler that it's constant. Use this function to read the CPU ID + * rather than directly reading processor_id or read_cpuid() directly. + */ +static inline u32 __attribute_const__ read_cpuid_id(void) +{ + return read_cpuid(MIDR_EL1); +} + /* * Represent a range of MIDR values for a given CPU model and a * range of variant/revision values. @@ -286,31 +296,6 @@ static inline bool midr_is_cpu_model_range(u32 midr, u= 32 model, u32 rv_min, return _model =3D=3D model && rv >=3D rv_min && rv <=3D rv_max; } =20 -static inline bool is_midr_in_range(u32 midr, struct midr_range const *ran= ge) -{ - return midr_is_cpu_model_range(midr, range->model, - range->rv_min, range->rv_max); -} - -static inline bool -is_midr_in_range_list(u32 midr, struct midr_range const *ranges) -{ - while (ranges->model) - if (is_midr_in_range(midr, ranges++)) - return true; - return false; -} - -/* - * The CPU ID never changes at run time, so we might as well tell the - * compiler that it's constant. Use this function to read the CPU ID - * rather than directly reading processor_id or read_cpuid() directly. - */ -static inline u32 __attribute_const__ read_cpuid_id(void) -{ - return read_cpuid(MIDR_EL1); -} - struct target_impl_cpu { u64 midr; u64 revidr; @@ -318,6 +303,7 @@ struct target_impl_cpu { }; =20 bool cpu_errata_set_target_impl(u64 num, void *impl_cpus); +bool is_midr_in_range_list(struct midr_range const *ranges); =20 static inline u64 __attribute_const__ read_cpuid_mpidr(void) { diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/incl= ude/asm/cpufeatures.h index 06fc0479a23f..751ca35386b0 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -495,6 +495,7 @@ #define X86_FEATURE_TSA_SQ_NO (21*32+11) /* AMD CPU not vulnerable to TSA= -SQ */ #define X86_FEATURE_TSA_L1_NO (21*32+12) /* AMD CPU not vulnerable to TSA= -L1 */ #define X86_FEATURE_CLEAR_CPU_BUF_VM (21*32+13) /* Clear CPU buffers using= VERW before VMRUN */ +#define X86_FEATURE_IBPB_EXIT_TO_USER (21*32+14) /* Use IBPB on exit-to-us= erspace, see VMSCAPE bug */ =20 /* * BUG word(s) @@ -551,4 +552,5 @@ #define X86_BUG_ITS X86_BUG( 1*32+ 7) /* "its" CPU is affected by Indire= ct Target Selection */ #define X86_BUG_ITS_NATIVE_ONLY X86_BUG( 1*32+ 8) /* "its_native_only" CP= U is affected by ITS, VMX is not affected */ #define X86_BUG_TSA X86_BUG( 1*32+ 9) /* "tsa" CPU is affected by Transi= ent Scheduler Attacks */ +#define X86_BUG_VMSCAPE X86_BUG( 1*32+10) /* "vmscape" CPU is affected b= y VMSCAPE attacks from guests */ #endif /* _ASM_X86_CPUFEATURES_H */ --=20 2.43.0