Document CSI HW block found in Tegra20 and Tegra30 SoC.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
.../display/tegra/nvidia,tegra20-csi.yaml | 135 ++++++++++++++++++
1 file changed, 135 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml
new file mode 100644
index 000000000000..817b3097846b
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-csi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra20 CSI controller
+
+maintainers:
+ - Svyatoslav Ryhel <clamor95@gmail.com>
+
+properties:
+ compatible:
+ enum:
+ - nvidia,tegra20-csi
+ - nvidia,tegra30-csi
+
+ reg:
+ maxItems: 1
+
+ clocks: true
+ clock-names: true
+
+ avdd-dsi-csi-supply:
+ description: DSI/CSI power supply. Must supply 1.2 V.
+
+ power-domains:
+ maxItems: 1
+
+ "#nvidia,mipi-calibrate-cells":
+ description:
+ The number of cells in a MIPI calibration specifier. Should be 1.
+ The single cell specifies an id of the pad that need to be
+ calibrated for a given device. Valid pad ids for receiver would be
+ 0 for CSI-A; 1 for CSI-B; 2 for DSI-A and 3 for DSI-B.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ const: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+patternProperties:
+ "^channel@[0-1]$":
+ type: object
+ description: channel 0 represents CSI-A and 1 represents CSI-B
+ additionalProperties: false
+
+ properties:
+ reg:
+ maximum: 1
+
+ nvidia,mipi-calibrate:
+ description: Should contain a phandle and a specifier specifying
+ which pad is used by this CSI channel and needs to be calibrated.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: port receiving the video stream from the sensor
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ required:
+ - data-lanes
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: port sending the video stream to the VI
+
+ required:
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - port@0
+ - port@1
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra20-csi
+ then:
+ properties:
+ clocks:
+ items:
+ - description: module clock
+
+ clock-names: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra30-csi
+ then:
+ properties:
+ clocks:
+ items:
+ - description: module clock
+ - description: PAD A clock
+ - description: PAD B clock
+
+ clock-names:
+ items:
+ - const: csi
+ - const: csia-pad
+ - const: csib-pad
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - power-domains
+ - "#address-cells"
+ - "#size-cells"
+
+# see nvidia,tegra20-vi.yaml for an example
--
2.48.1On Thu, Sep 25, 2025 at 06:16:46PM +0300, Svyatoslav Ryhel wrote:
> Document CSI HW block found in Tegra20 and Tegra30 SoC.
>
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
> .../display/tegra/nvidia,tegra20-csi.yaml | 135 ++++++++++++++++++
> 1 file changed, 135 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml
> new file mode 100644
> index 000000000000..817b3097846b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml
> @@ -0,0 +1,135 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-csi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra20 CSI controller
> +
> +maintainers:
> + - Svyatoslav Ryhel <clamor95@gmail.com>
> +
> +properties:
> + compatible:
> + enum:
> + - nvidia,tegra20-csi
> + - nvidia,tegra30-csi
> +
> + reg:
> + maxItems: 1
> +
> + clocks: true
> + clock-names: true
> +
> + avdd-dsi-csi-supply:
> + description: DSI/CSI power supply. Must supply 1.2 V.
> +
> + power-domains:
> + maxItems: 1
> +
> + "#nvidia,mipi-calibrate-cells":
> + description:
> + The number of cells in a MIPI calibration specifier. Should be 1.
> + The single cell specifies an id of the pad that need to be
> + calibrated for a given device. Valid pad ids for receiver would be
> + 0 for CSI-A; 1 for CSI-B; 2 for DSI-A and 3 for DSI-B.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + const: 1
Sorry I didn't bring this up before, but is this ever not 1? If it is
fixed, then you don't really need the property. I prefer it just be
fixed rather than getting a bunch of vendor specific #foo-cells.
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
> +
> +patternProperties:
> + "^channel@[0-1]$":
> + type: object
> + description: channel 0 represents CSI-A and 1 represents CSI-B
> + additionalProperties: false
> +
> + properties:
> + reg:
> + maximum: 1
> +
> + nvidia,mipi-calibrate:
> + description: Should contain a phandle and a specifier specifying
> + which pad is used by this CSI channel and needs to be calibrated.
> + $ref: /schemas/types.yaml#/definitions/phandle-array
Sounds like only one entry? Then 'maxItems: 1' is needed. If you drop
#nvidia,mipi-calibrate-cells, then you need to define the arg size too:
items:
- items:
- description: phandle to ...
- description: what the arg contains.
чт, 2 жовт. 2025 р. о 04:52 Rob Herring <robh@kernel.org> пише: > > On Thu, Sep 25, 2025 at 06:16:46PM +0300, Svyatoslav Ryhel wrote: > > Document CSI HW block found in Tegra20 and Tegra30 SoC. > > > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> > > --- > > .../display/tegra/nvidia,tegra20-csi.yaml | 135 ++++++++++++++++++ > > 1 file changed, 135 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml > > > > diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml > > new file mode 100644 > > index 000000000000..817b3097846b > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml > > @@ -0,0 +1,135 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-csi.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: NVIDIA Tegra20 CSI controller > > + > > +maintainers: > > + - Svyatoslav Ryhel <clamor95@gmail.com> > > + > > +properties: > > + compatible: > > + enum: > > + - nvidia,tegra20-csi > > + - nvidia,tegra30-csi > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: true > > + clock-names: true > > + > > + avdd-dsi-csi-supply: > > + description: DSI/CSI power supply. Must supply 1.2 V. > > + > > + power-domains: > > + maxItems: 1 > > + > > + "#nvidia,mipi-calibrate-cells": > > + description: > > + The number of cells in a MIPI calibration specifier. Should be 1. > > + The single cell specifies an id of the pad that need to be > > + calibrated for a given device. Valid pad ids for receiver would be > > + 0 for CSI-A; 1 for CSI-B; 2 for DSI-A and 3 for DSI-B. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + const: 1 > > Sorry I didn't bring this up before, but is this ever not 1? If it is > fixed, then you don't really need the property. I prefer it just be > fixed rather than getting a bunch of vendor specific #foo-cells. > This is not an introduction of property, such property already exists in Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml and is used in multiple device trees. As I have told before, in case of Tegra30 and Tegra20 CSI block combines mipi calibration function and CSI function, in Tegra114+ mipi calibration got a dedicated hardware block which is already supported. This property here is used to align with mipi-calibration logic used by Tegra114+ > > > + > > + "#address-cells": > > + const: 1 > > + > > + "#size-cells": > > + const: 0 > > + > > +patternProperties: > > + "^channel@[0-1]$": > > + type: object > > + description: channel 0 represents CSI-A and 1 represents CSI-B > > + additionalProperties: false > > + > > + properties: > > + reg: > > + maximum: 1 > > + > > + nvidia,mipi-calibrate: > > + description: Should contain a phandle and a specifier specifying > > + which pad is used by this CSI channel and needs to be calibrated. > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > Sounds like only one entry? Then 'maxItems: 1' is needed. If you drop > #nvidia,mipi-calibrate-cells, then you need to define the arg size too: > > items: > - items: > - description: phandle to ... > - description: what the arg contains. >
On Thu, Oct 02, 2025 at 08:14:22AM +0300, Svyatoslav Ryhel wrote: > чт, 2 жовт. 2025 р. о 04:52 Rob Herring <robh@kernel.org> пише: > > > > On Thu, Sep 25, 2025 at 06:16:46PM +0300, Svyatoslav Ryhel wrote: > > > Document CSI HW block found in Tegra20 and Tegra30 SoC. > > > > > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> > > > --- > > > .../display/tegra/nvidia,tegra20-csi.yaml | 135 ++++++++++++++++++ > > > 1 file changed, 135 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml > > > new file mode 100644 > > > index 000000000000..817b3097846b > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml > > > @@ -0,0 +1,135 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-csi.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: NVIDIA Tegra20 CSI controller > > > + > > > +maintainers: > > > + - Svyatoslav Ryhel <clamor95@gmail.com> > > > + > > > +properties: > > > + compatible: > > > + enum: > > > + - nvidia,tegra20-csi > > > + - nvidia,tegra30-csi > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + clocks: true > > > + clock-names: true > > > + > > > + avdd-dsi-csi-supply: > > > + description: DSI/CSI power supply. Must supply 1.2 V. > > > + > > > + power-domains: > > > + maxItems: 1 > > > + > > > + "#nvidia,mipi-calibrate-cells": > > > + description: > > > + The number of cells in a MIPI calibration specifier. Should be 1. > > > + The single cell specifies an id of the pad that need to be > > > + calibrated for a given device. Valid pad ids for receiver would be > > > + 0 for CSI-A; 1 for CSI-B; 2 for DSI-A and 3 for DSI-B. > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > + const: 1 > > > > Sorry I didn't bring this up before, but is this ever not 1? If it is > > fixed, then you don't really need the property. I prefer it just be > > fixed rather than getting a bunch of vendor specific #foo-cells. > > > > This is not an introduction of property, such property already exists > in Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml > and is used in multiple device trees. As I have told before, in case > of Tegra30 and Tegra20 CSI block combines mipi calibration function > and CSI function, in Tegra114+ mipi calibration got a dedicated > hardware block which is already supported. This property here is used > to align with mipi-calibration logic used by Tegra114+ Okay. You will have to continue to tell me again if my past questions are not addressed in the commit message. A review only last week was 100+ patches ago. Don't expect I'll remember nor go re-read prior versions. Ideally, we don't define the type of a property more than once. So this should really first be moved to its own shared schema that's referenced here and in the original user. Then it is perfectly clear reading the patches that this is not a new property. Rob
пн, 6 жовт. 2025 р. о 23:31 Rob Herring <robh@kernel.org> пише: > > On Thu, Oct 02, 2025 at 08:14:22AM +0300, Svyatoslav Ryhel wrote: > > чт, 2 жовт. 2025 р. о 04:52 Rob Herring <robh@kernel.org> пише: > > > > > > On Thu, Sep 25, 2025 at 06:16:46PM +0300, Svyatoslav Ryhel wrote: > > > > Document CSI HW block found in Tegra20 and Tegra30 SoC. > > > > > > > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> > > > > --- > > > > .../display/tegra/nvidia,tegra20-csi.yaml | 135 ++++++++++++++++++ > > > > 1 file changed, 135 insertions(+) > > > > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml > > > > > > > > diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml > > > > new file mode 100644 > > > > index 000000000000..817b3097846b > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml > > > > @@ -0,0 +1,135 @@ > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > +%YAML 1.2 > > > > +--- > > > > +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-csi.yaml# > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > + > > > > +title: NVIDIA Tegra20 CSI controller > > > > + > > > > +maintainers: > > > > + - Svyatoslav Ryhel <clamor95@gmail.com> > > > > + > > > > +properties: > > > > + compatible: > > > > + enum: > > > > + - nvidia,tegra20-csi > > > > + - nvidia,tegra30-csi > > > > + > > > > + reg: > > > > + maxItems: 1 > > > > + > > > > + clocks: true > > > > + clock-names: true > > > > + > > > > + avdd-dsi-csi-supply: > > > > + description: DSI/CSI power supply. Must supply 1.2 V. > > > > + > > > > + power-domains: > > > > + maxItems: 1 > > > > + > > > > + "#nvidia,mipi-calibrate-cells": > > > > + description: > > > > + The number of cells in a MIPI calibration specifier. Should be 1. > > > > + The single cell specifies an id of the pad that need to be > > > > + calibrated for a given device. Valid pad ids for receiver would be > > > > + 0 for CSI-A; 1 for CSI-B; 2 for DSI-A and 3 for DSI-B. > > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > > + const: 1 > > > > > > Sorry I didn't bring this up before, but is this ever not 1? If it is > > > fixed, then you don't really need the property. I prefer it just be > > > fixed rather than getting a bunch of vendor specific #foo-cells. > > > > > > > This is not an introduction of property, such property already exists > > in Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml > > and is used in multiple device trees. As I have told before, in case > > of Tegra30 and Tegra20 CSI block combines mipi calibration function > > and CSI function, in Tegra114+ mipi calibration got a dedicated > > hardware block which is already supported. This property here is used > > to align with mipi-calibration logic used by Tegra114+ > > Okay. > > You will have to continue to tell me again if my past questions are not > addressed in the commit message. A review only last week was 100+ > patches ago. Don't expect I'll remember nor go re-read prior versions. > That is not a problem, I did not meant to offend you. I will add info into commit message. > Ideally, we don't define the type of a property more than once. So this > should really first be moved to its own shared schema that's referenced > here and in the original user. Then it is perfectly clear reading the > patches that this is not a new property. > I am not sure that creating a dedicated shared schema for a single properly which is used by 2 schemas worth it, though, if it is preferred, may the refactoring be done in followups later? > Rob
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