This patch series addresses issues and optimizations in the Xilinx
AXI DMA driver:
1. Fix channel idle state management in the interrupt handler.
2. Enable transfer chaining by removing unnecessary idle restrictions.
3. Optimize control register writes and channel start logic.

Note: The patches in this series were part of following IRQ coalescing
series which is under discussion:
https://lore.kernel.org/all/20250710101229.804183-1-suraj.gupta2@amd.com/

Suraj Gupta (3):
  dmaengine: xilinx_dma: Fix channel idle state management in interrupt
    handler
  dmaengine: xilinx_dma: Enable transfer chaining by removing idle
    restriction
  dmaengine: xilinx_dma: Optimize control register write and channel
    start logic in xilinx_dma_start_transfer

 drivers/dma/xilinx/xilinx_dma.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

-- 
2.25.1