This patch set adds support for address translation using ACPI PRM and
enables this for AMD Zen5 platforms. This is another new appoach in
response to earlier attempts to implement CXL address translation:

 * v1: [1] and the comments on it, esp. Dan's [2],
 * v2: [3] and comments on [4], esp. Dave's [5]

This version 3 addresses the requests to reduce the number of patches
to a minimum and also to remove platform specific implementations
allowing the Documentation of CXL Address Translation Support in the
Kernel's "Compute Express Link: Linux Conventions" document and an
update of the CXL specification in the longterm. This patch submission
will be the base for a documention patch that describes CXL Address
Translation support accordingly. The documentation patch will be sent
in the very next step.

The CXL driver currently does not implement address translation which
assumes the host physical addresses (HPA) and system physical
addresses (SPA) are equal.

Systems with different HPA and SPA addresses need address translation.
If this is the case, the hardware addresses esp. used in the HDM
decoder configurations are different to the system's or parent port
address ranges. E.g. AMD Zen5 systems may be configured to use
'Normalized addresses'. Then, CXL endpoints have their own physical
address base which is not the same as the SPA used by the CXL host
bridge. Thus, addresses need to be translated from the endpoint's to
its CXL host bridge's address range.

To enable address translation, the endpoint's HPA range must be
translated to the CXL host bridge's address range. A callback is
introduced to translate a decoder's HPA to the next parent port's
address range. This allows the enablement of address translation for
individual ports as needed. The callback is then used to determine the
region parameters which includes the SPA translated address range of
the endpoint decoder and the interleaving configuration. This is
stored in struct cxl_region which allows an endpoint decoder to
determine that parameters based on its assigned region.

Note that only auto-discovery of decoders is supported. Thus, decoders
are locked and cannot be configured manually.

Finally, Zen5 address translation is enabled using ACPI PRMT.

This series bases on cxl/next.

V3:
 * rebased onto cxl/next,
 * complete rework to reduce number of required changes/patches and to
   remove platform specific code (Dan and Dave),
 * changed implementation allowing to add address translation to the
   CXL specification (documention patch in preparation),
 * simplified and generalized determination of interleaving
   parameters using the address translation callback,
 * depend only on the existence of the ACPI PRM GUID for CXL Address
   Translation enablement, removed platform checks,
 * small changes to region code only which does not require a full
   rework and refactoring of the code, just separating region
   parameter setup and region construction,
 * moved code to new core/atl.c file,
 * fixed subsys_initcall order dependency of EFI runtime services
   (Gregory and Joshua),

V2:
 * rebased onto cxl/next,
 * split of v1 in two parts:
   * removed cleanups and updates from this series to post them as a
     separate series (Dave),
   * this part 2 applies on top of part 1, v3,
 * added tags to SOB chain,
 * reworked architecture, vendor and platform setup (Jonathan):
   * added patch "cxl/x86: Prepare for architectural platform setup",
   * added function arch_cxl_port_platform_setup() plus a __weak
     versions for archs other than x86,
   * moved code to core/x86,
 * added comment to cxl_to_hpa_fn (Ben),
 * updated year in copyright statement (Ben),
 * cxl_port_calc_hpa(): Removed HPA check for zero (Jonathan), return
   1 if modified,
 * cxl_port_calc_pos(): Updated description and wording (Ben),
 * added sereral patches around interleaving and SPA calculation in
   cxl_endpoint_decoder_initialize(),
 * reworked iterator in cxl_endpoint_decoder_initialize() (Gregory),
 * fixed region interleaving parameters() (Alison),
 * fixed check in cxl_region_attach() (Alison),
 * Clarified in coverletter that not all ports in a system must
   implement the to_hpa() callback (Terry).

[1] https://lore.kernel.org/linux-cxl/20240701174754.967954-1-rrichter@amd.com/
[2] https://lore.kernel.org/linux-cxl/669086821f136_5fffa29473@dwillia2-xfh.jf.intel.com.notmuch/
[3] https://patchwork.kernel.org/project/cxl/cover/20250218132356.1809075-1-rrichter@amd.com/
[4] https://patchwork.kernel.org/project/cxl/cover/20250715191143.1023512-1-rrichter@amd.com/
[5] https://lore.kernel.org/all/78284b12-3e0b-4758-af18-397f32136c3f@intel.com/

Robert Richter (11):
  cxl/region: Store root decoder in struct cxl_region
  cxl/region: Store HPA range in struct cxl_region
  cxl/region: Rename misleading variable name @hpa to @range
  cxl/region: Add @range argument to function cxl_find_root_decoder()
  cxl/region: Add @range argument to function cxl_calc_interleave_pos()
  cxl/region: Separate region parameter setup and region construction
  cxl: Introduce callback to translate a decoder's HPA to the next
    parent port
  cxl/region: Implement endpoint decoder address translation
  cxl/region: Lock decoders that need address translation
  cxl/acpi: Prepare use of EFI runtime services
  cxl: Enable AMD Zen5 address translation using ACPI PRMT

 drivers/cxl/Kconfig       |   4 +
 drivers/cxl/acpi.c        |   8 +-
 drivers/cxl/core/Makefile |   1 +
 drivers/cxl/core/atl.c    | 138 ++++++++++++++++++++++
 drivers/cxl/core/core.h   |   1 +
 drivers/cxl/core/port.c   |   8 ++
 drivers/cxl/core/region.c | 239 ++++++++++++++++++++++++++++++--------
 drivers/cxl/cxl.h         |  17 +++
 8 files changed, 368 insertions(+), 48 deletions(-)
 create mode 100644 drivers/cxl/core/atl.c


base-commit: 561c4e30bff93b3c33e694a459f8580f8a6b3c8c
-- 
2.39.5

On 9/12/25 7:45 AM, Robert Richter wrote:
> This patch set adds support for address translation using ACPI PRM and
> enables this for AMD Zen5 platforms. This is another new appoach in
> response to earlier attempts to implement CXL address translation:
> 
>  * v1: [1] and the comments on it, esp. Dan's [2],
>  * v2: [3] and comments on [4], esp. Dave's [5]
> 
> This version 3 addresses the requests to reduce the number of patches
> to a minimum and also to remove platform specific implementations
> allowing the Documentation of CXL Address Translation Support in the
> Kernel's "Compute Express Link: Linux Conventions" document and an
> update of the CXL specification in the longterm. This patch submission
> will be the base for a documention patch that describes CXL Address
> Translation support accordingly. The documentation patch will be sent
> in the very next step.
> 
> The CXL driver currently does not implement address translation which
> assumes the host physical addresses (HPA) and system physical
> addresses (SPA) are equal.
> 
> Systems with different HPA and SPA addresses need address translation.
> If this is the case, the hardware addresses esp. used in the HDM
> decoder configurations are different to the system's or parent port
> address ranges. E.g. AMD Zen5 systems may be configured to use
> 'Normalized addresses'. Then, CXL endpoints have their own physical
> address base which is not the same as the SPA used by the CXL host
> bridge. Thus, addresses need to be translated from the endpoint's to
> its CXL host bridge's address range.
> 
> To enable address translation, the endpoint's HPA range must be
> translated to the CXL host bridge's address range. A callback is
> introduced to translate a decoder's HPA to the next parent port's
> address range. This allows the enablement of address translation for
> individual ports as needed. The callback is then used to determine the
> region parameters which includes the SPA translated address range of
> the endpoint decoder and the interleaving configuration. This is
> stored in struct cxl_region which allows an endpoint decoder to
> determine that parameters based on its assigned region.
> 
> Note that only auto-discovery of decoders is supported. Thus, decoders
> are locked and cannot be configured manually.

Hi Robert, thanks for reworking this.

What happens with the manual configured path if only auto-discovery is supported? Things don't work? It works with no translation needed? Platform will lock all decoders and not allow manual configuration for CXL devices?

DJ

> 
> Finally, Zen5 address translation is enabled using ACPI PRMT.
> 
> This series bases on cxl/next.
> 
> V3:
>  * rebased onto cxl/next,
>  * complete rework to reduce number of required changes/patches and to
>    remove platform specific code (Dan and Dave),
>  * changed implementation allowing to add address translation to the
>    CXL specification (documention patch in preparation),
>  * simplified and generalized determination of interleaving
>    parameters using the address translation callback,
>  * depend only on the existence of the ACPI PRM GUID for CXL Address
>    Translation enablement, removed platform checks,
>  * small changes to region code only which does not require a full
>    rework and refactoring of the code, just separating region
>    parameter setup and region construction,
>  * moved code to new core/atl.c file,
>  * fixed subsys_initcall order dependency of EFI runtime services
>    (Gregory and Joshua),
> 
> V2:
>  * rebased onto cxl/next,
>  * split of v1 in two parts:
>    * removed cleanups and updates from this series to post them as a
>      separate series (Dave),
>    * this part 2 applies on top of part 1, v3,
>  * added tags to SOB chain,
>  * reworked architecture, vendor and platform setup (Jonathan):
>    * added patch "cxl/x86: Prepare for architectural platform setup",
>    * added function arch_cxl_port_platform_setup() plus a __weak
>      versions for archs other than x86,
>    * moved code to core/x86,
>  * added comment to cxl_to_hpa_fn (Ben),
>  * updated year in copyright statement (Ben),
>  * cxl_port_calc_hpa(): Removed HPA check for zero (Jonathan), return
>    1 if modified,
>  * cxl_port_calc_pos(): Updated description and wording (Ben),
>  * added sereral patches around interleaving and SPA calculation in
>    cxl_endpoint_decoder_initialize(),
>  * reworked iterator in cxl_endpoint_decoder_initialize() (Gregory),
>  * fixed region interleaving parameters() (Alison),
>  * fixed check in cxl_region_attach() (Alison),
>  * Clarified in coverletter that not all ports in a system must
>    implement the to_hpa() callback (Terry).
> 
> [1] https://lore.kernel.org/linux-cxl/20240701174754.967954-1-rrichter@amd.com/
> [2] https://lore.kernel.org/linux-cxl/669086821f136_5fffa29473@dwillia2-xfh.jf.intel.com.notmuch/
> [3] https://patchwork.kernel.org/project/cxl/cover/20250218132356.1809075-1-rrichter@amd.com/
> [4] https://patchwork.kernel.org/project/cxl/cover/20250715191143.1023512-1-rrichter@amd.com/
> [5] https://lore.kernel.org/all/78284b12-3e0b-4758-af18-397f32136c3f@intel.com/
> 
> Robert Richter (11):
>   cxl/region: Store root decoder in struct cxl_region
>   cxl/region: Store HPA range in struct cxl_region
>   cxl/region: Rename misleading variable name @hpa to @range
>   cxl/region: Add @range argument to function cxl_find_root_decoder()
>   cxl/region: Add @range argument to function cxl_calc_interleave_pos()
>   cxl/region: Separate region parameter setup and region construction
>   cxl: Introduce callback to translate a decoder's HPA to the next
>     parent port
>   cxl/region: Implement endpoint decoder address translation
>   cxl/region: Lock decoders that need address translation
>   cxl/acpi: Prepare use of EFI runtime services
>   cxl: Enable AMD Zen5 address translation using ACPI PRMT
> 
>  drivers/cxl/Kconfig       |   4 +
>  drivers/cxl/acpi.c        |   8 +-
>  drivers/cxl/core/Makefile |   1 +
>  drivers/cxl/core/atl.c    | 138 ++++++++++++++++++++++
>  drivers/cxl/core/core.h   |   1 +
>  drivers/cxl/core/port.c   |   8 ++
>  drivers/cxl/core/region.c | 239 ++++++++++++++++++++++++++++++--------
>  drivers/cxl/cxl.h         |  17 +++
>  8 files changed, 368 insertions(+), 48 deletions(-)
>  create mode 100644 drivers/cxl/core/atl.c
> 
> 
> base-commit: 561c4e30bff93b3c33e694a459f8580f8a6b3c8c

On 12.09.25 08:45:37, Dave Jiang wrote:
> 
> 
> On 9/12/25 7:45 AM, Robert Richter wrote:
> > This patch set adds support for address translation using ACPI PRM and
> > enables this for AMD Zen5 platforms. This is another new appoach in
> > response to earlier attempts to implement CXL address translation:
> > 
> >  * v1: [1] and the comments on it, esp. Dan's [2],
> >  * v2: [3] and comments on [4], esp. Dave's [5]
> > 
> > This version 3 addresses the requests to reduce the number of patches
> > to a minimum and also to remove platform specific implementations
> > allowing the Documentation of CXL Address Translation Support in the
> > Kernel's "Compute Express Link: Linux Conventions" document and an
> > update of the CXL specification in the longterm. This patch submission
> > will be the base for a documention patch that describes CXL Address
> > Translation support accordingly. The documentation patch will be sent
> > in the very next step.
> > 
> > The CXL driver currently does not implement address translation which
> > assumes the host physical addresses (HPA) and system physical
> > addresses (SPA) are equal.
> > 
> > Systems with different HPA and SPA addresses need address translation.
> > If this is the case, the hardware addresses esp. used in the HDM
> > decoder configurations are different to the system's or parent port
> > address ranges. E.g. AMD Zen5 systems may be configured to use
> > 'Normalized addresses'. Then, CXL endpoints have their own physical
> > address base which is not the same as the SPA used by the CXL host
> > bridge. Thus, addresses need to be translated from the endpoint's to
> > its CXL host bridge's address range.
> > 
> > To enable address translation, the endpoint's HPA range must be
> > translated to the CXL host bridge's address range. A callback is
> > introduced to translate a decoder's HPA to the next parent port's
> > address range. This allows the enablement of address translation for
> > individual ports as needed. The callback is then used to determine the
> > region parameters which includes the SPA translated address range of
> > the endpoint decoder and the interleaving configuration. This is
> > stored in struct cxl_region which allows an endpoint decoder to
> > determine that parameters based on its assigned region.
> > 
> > Note that only auto-discovery of decoders is supported. Thus, decoders
> > are locked and cannot be configured manually.
> 
> Hi Robert, thanks for reworking this.
> 

> What happens with the manual configured path if only auto-discovery
> is supported? Things don't work? It works with no translation
> needed? Platform will lock all decoders and not allow manual
> configuration for CXL devices?

Endpoints, root ports and bridges are always pre-configured by
firmware in this case. A manual setup is not supported. That is why
the endpoints are locked to prevent the kernel from reconfiguring the
decoders, see:

 [PATCH v3 09/11] cxl/region: Lock decoders that need address translation

-Robert

On Fri, Sep 12, 2025 at 04:45:02PM +0200, Robert Richter wrote:
> This patch set adds support for address translation using ACPI PRM and
> enables this for AMD Zen5 platforms. This is another new appoach in
> response to earlier attempts to implement CXL address translation:
>

For the series:

Tested-by: Gregory Price <gourry@gourry.net>