Hi all,

With the introduction of the Icicle Kit with the production device
(MPFS250T) to the market, it's necessary to distinguish it from the
engineering sample (-es) variant. This is because engineering samples
cannot write to flash from the MSS, as noted in the PolarFire SoC
FPGA ES errata.

This series adds a common board DTSI for the Icicle Kit, containing
hardware shared by both the engineering sample and production
versions, as well as a DTS for each Icicle Kit variant.

The last two patches add support for the PolarFire SoC Discovery Kit
board.

Changes since v2:
 - rename ccc clock to clock-cccref to match fixed clock binding

Changes since v1:
 - fix order of properties in mailbox nodes
 - drop redundant status property from ddrc_cache nodes
 - fix lowercase hex in reserved memory regions

Thanks,
Valentina

Valentina Fernandez (6):
  riscv: dts: microchip: add common board dtsi for icicle kit variants
  dt-bindings: riscv: microchip: document icicle kit with production
    device
  riscv: dts: microchip: add icicle kit with production device
  riscv: dts: microchip: rename icicle kit ccc clock and other minor
    fixes
  dt-bindings: riscv: microchip: document Discovery Kit
  riscv: dts: microchip: add a device tree for Discovery Kit

 .../devicetree/bindings/riscv/microchip.yaml  |  13 +
 arch/riscv/boot/dts/microchip/Makefile        |   2 +
 .../dts/microchip/mpfs-disco-kit-fabric.dtsi  |  58 ++++
 .../boot/dts/microchip/mpfs-disco-kit.dts     | 190 +++++++++++++
 .../dts/microchip/mpfs-icicle-kit-common.dtsi | 249 ++++++++++++++++++
 .../dts/microchip/mpfs-icicle-kit-fabric.dtsi |  25 +-
 .../dts/microchip/mpfs-icicle-kit-prod.dts    |  23 ++
 .../boot/dts/microchip/mpfs-icicle-kit.dts    | 244 +----------------
 8 files changed, 559 insertions(+), 245 deletions(-)
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts

-- 
2.34.1

On Mon, Sep 08, 2025 at 12:57:26PM +0100, Valentina Fernandez wrote:
> Hi all,
> 
> With the introduction of the Icicle Kit with the production device
> (MPFS250T) to the market, it's necessary to distinguish it from the
> engineering sample (-es) variant. This is because engineering samples
> cannot write to flash from the MSS, as noted in the PolarFire SoC
> FPGA ES errata.
> 
> This series adds a common board DTSI for the Icicle Kit, containing
> hardware shared by both the engineering sample and production
> versions, as well as a DTS for each Icicle Kit variant.
> 
> The last two patches add support for the PolarFire SoC Discovery Kit
> board.
> 
> Changes since v2:
>  - rename ccc clock to clock-cccref to match fixed clock binding
> 
> Changes since v1:
>  - fix order of properties in mailbox nodes
>  - drop redundant status property from ddrc_cache nodes
>  - fix lowercase hex in reserved memory regions

I've replaced v1 with this version in my tree.