From nobody Wed Sep 10 02:03:22 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CB9521B9DA; Mon, 8 Sep 2025 11:48:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757332136; cv=none; b=AbF1CFcdYS7QNQthlKDElZA3M7s+fvYf1bMwcoySL1DoFy2ZvUjtMW+BljI79+wY98gIHiOqc7WjenRjBeLkK/nAXkITACMC4Hz5P7VMxLwrxquqpRrMSA+6SiuqqAIkGCyO7QPyzKsusIgqdxRUJ6ugD/IHTijSloE5A8TIxzs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757332136; c=relaxed/simple; bh=TB1dOd76PEJ5mgVTi3H1IPzDArXUmTgjE1tKSSsdtws=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=S3/t5SnS/IW64B+qZ4tBYpMXPcrL/78CTTh/BaKiTW+0FJG8/YGgZI3JxEmiaiH4H51rz16jP3Bcja/lRPDdulCni2UV/BkbRfYe9FjNldnLemfpZCu35vUvamAEd4zEymLpv/5RA5balCWk3+uRpOtBNlBBqLi+cKaoPsi96nw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=f1oMNSY7; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="f1oMNSY7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1757332134; x=1788868134; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TB1dOd76PEJ5mgVTi3H1IPzDArXUmTgjE1tKSSsdtws=; b=f1oMNSY7HH2uZaHMtdWm40U6stBNytnNRTOEjtNIf7ZELNXxaFjJhUJI WQ4r333woY8p5NLlnW5GJ5uAhL1pKHvWtsFb4+FT2lDEPoBc8/DiiRJty gqxvueon6SdDaNZQ5JrxnmoKQGA7NlivPhPNISPnmnGJOd1PB9MHUxsvl NEHn6KDm7ksZbzR8MUskmN1iZcL4ijnJg8CRj9/8dy1PD2+6h6OL2cJ4n /EejweMqER9i/8s4StN9uxkSOm2y0iktOk5iz2dRwVudi1dWmys7KXhaJ PBS0l3RiCtFXDiyb485q769GlS0tV9xlDtrc3U1r9Z+balcMGzsDvnJde A==; X-CSE-ConnectionGUID: vDOPHTnsQiaqmkXt9yltVw== X-CSE-MsgGUID: GG+dxavVTLWTh8ASbpZspA== X-IronPort-AV: E=Sophos;i="6.18,248,1751266800"; d="scan'208";a="45634875" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 08 Sep 2025 04:48:52 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Mon, 8 Sep 2025 04:48:37 -0700 Received: from valentina.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 8 Sep 2025 04:48:34 -0700 From: Valentina Fernandez To: , , , , , , , , CC: , , Subject: [PATCH v3 1/6] riscv: dts: microchip: add common board dtsi for icicle kit variants Date: Mon, 8 Sep 2025 12:57:27 +0100 Message-ID: <20250908115732.31092-2-valentina.fernandezalanis@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908115732.31092-1-valentina.fernandezalanis@microchip.com> References: <20250908115732.31092-1-valentina.fernandezalanis@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for supporting the Icicle Kit with production silicon, add a common board dtsi for the icicle kit with hardware shared by both the engineering sample and production versions. Signed-off-by: Valentina Fernandez --- .../dts/microchip/mpfs-icicle-kit-common.dtsi | 247 ++++++++++++++++++ .../boot/dts/microchip/mpfs-icicle-kit.dts | 241 +---------------- 2 files changed, 248 insertions(+), 240 deletions(-) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dt= si diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi new file mode 100644 index 000000000000..eafea3b69cd7 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2025 Microchip Technology Inc */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-icicle-kit-fabric.dtsi" +#include +#include + +/ { + aliases { + ethernet0 =3D &mac1; + serial0 =3D &mmuart0; + serial1 =3D &mmuart1; + serial2 =3D &mmuart2; + serial3 =3D &mmuart3; + serial4 =3D &mmuart4; + }; + + chosen { + stdout-path =3D "serial1:115200n8"; + }; + + leds { + compatible =3D "gpio-leds"; + + led-1 { + gpios =3D <&gpio2 16 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led1"; + }; + + led-2 { + gpios =3D <&gpio2 17 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led2"; + }; + + led-3 { + gpios =3D <&gpio2 18 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led3"; + }; + + led-4 { + gpios =3D <&gpio2 19 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led4"; + }; + }; + + ddrc_cache_lo: memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x40000000>; + status =3D "okay"; + }; + + ddrc_cache_hi: memory@1040000000 { + device_type =3D "memory"; + reg =3D <0x10 0x40000000 0x0 0x40000000>; + status =3D "okay"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + hss_payload: region@BFC00000 { + reg =3D <0x0 0xBFC00000 0x0 0x400000>; + no-map; + }; + }; +}; + +&core_pwm0 { + status =3D "okay"; +}; + +&gpio2 { + interrupts =3D <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; +}; + +&i2c1 { + status =3D "okay"; + + power-monitor@10 { + compatible =3D "microchip,pac1934"; + reg =3D <0x10>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + channel@1 { + reg =3D <0x1>; + shunt-resistor-micro-ohms =3D <10000>; + label =3D "VDDREG"; + }; + + channel@2 { + reg =3D <0x2>; + shunt-resistor-micro-ohms =3D <10000>; + label =3D "VDDA25"; + }; + + channel@3 { + reg =3D <0x3>; + shunt-resistor-micro-ohms =3D <10000>; + label =3D "VDD25"; + }; + + channel@4 { + reg =3D <0x4>; + shunt-resistor-micro-ohms =3D <10000>; + label =3D "VDDA_REG"; + }; + }; +}; + +&i2c2 { + status =3D "okay"; +}; + +&mac0 { + phy-mode =3D "sgmii"; + phy-handle =3D <&phy0>; + status =3D "okay"; +}; + +&mac1 { + phy-mode =3D "sgmii"; + phy-handle =3D <&phy1>; + status =3D "okay"; + + phy1: ethernet-phy@9 { + reg =3D <9>; + }; + + phy0: ethernet-phy@8 { + reg =3D <8>; + }; +}; + +&mbox { + status =3D "okay"; +}; + +&mmc { + bus-width =3D <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status =3D "okay"; +}; + +&mmuart1 { + status =3D "okay"; +}; + +&mmuart2 { + status =3D "okay"; +}; + +&mmuart3 { + status =3D "okay"; +}; + +&mmuart4 { + status =3D "okay"; +}; + +&pcie { + status =3D "okay"; +}; + +&qspi { + status =3D "okay"; +}; + +&refclk { + clock-frequency =3D <125000000>; +}; + +&refclk_ccc { + clock-frequency =3D <50000000>; +}; + +&rtc { + status =3D "okay"; +}; + +&spi0 { + status =3D "okay"; +}; + +&spi1 { + status =3D "okay"; +}; + +&syscontroller { + status =3D "okay"; +}; + +&syscontroller_qspi { + /* + * The flash *is* there, but Icicle kits that have engineering sample + * silicon (write?) access to this flash to non-functional. The system + * controller itself can actually access it, but the MSS cannot write + * an image there. Instantiating a coreQSPI in the fabric & connecting + * it to the flash instead should work though. Pre-production or later + * silicon does not have this issue. + */ + status =3D "disabled"; + + sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT + compatible =3D "jedec,spi-nor"; + #address-cells =3D <1>; + #size-cells =3D <1>; + spi-max-frequency =3D <20000000>; + spi-rx-bus-width =3D <1>; + reg =3D <0>; + }; +}; + +&usb { + status =3D "okay"; + dr_mode =3D "host"; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv= /boot/dts/microchip/mpfs-icicle-kit.dts index f80df225f72b..2cb08ed0946d 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -3,249 +3,10 @@ =20 /dts-v1/; =20 -#include "mpfs.dtsi" -#include "mpfs-icicle-kit-fabric.dtsi" -#include -#include +#include "mpfs-icicle-kit-common.dtsi" =20 / { model =3D "Microchip PolarFire-SoC Icicle Kit"; compatible =3D "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpf= s-icicle-kit", "microchip,mpfs"; - - aliases { - ethernet0 =3D &mac1; - serial0 =3D &mmuart0; - serial1 =3D &mmuart1; - serial2 =3D &mmuart2; - serial3 =3D &mmuart3; - serial4 =3D &mmuart4; - }; - - chosen { - stdout-path =3D "serial1:115200n8"; - }; - - leds { - compatible =3D "gpio-leds"; - - led-1 { - gpios =3D <&gpio2 16 GPIO_ACTIVE_HIGH>; - color =3D ; - label =3D "led1"; - }; - - led-2 { - gpios =3D <&gpio2 17 GPIO_ACTIVE_HIGH>; - color =3D ; - label =3D "led2"; - }; - - led-3 { - gpios =3D <&gpio2 18 GPIO_ACTIVE_HIGH>; - color =3D ; - label =3D "led3"; - }; - - led-4 { - gpios =3D <&gpio2 19 GPIO_ACTIVE_HIGH>; - color =3D ; - label =3D "led4"; - }; - }; - - ddrc_cache_lo: memory@80000000 { - device_type =3D "memory"; - reg =3D <0x0 0x80000000 0x0 0x40000000>; - status =3D "okay"; - }; - - ddrc_cache_hi: memory@1040000000 { - device_type =3D "memory"; - reg =3D <0x10 0x40000000 0x0 0x40000000>; - status =3D "okay"; - }; - - reserved-memory { - #address-cells =3D <2>; - #size-cells =3D <2>; - ranges; - - hss_payload: region@BFC00000 { - reg =3D <0x0 0xBFC00000 0x0 0x400000>; - no-map; - }; - }; -}; - -&core_pwm0 { - status =3D "okay"; -}; - -&gpio2 { - interrupts =3D <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>; - status =3D "okay"; -}; - -&i2c0 { - status =3D "okay"; -}; - -&i2c1 { - status =3D "okay"; - - power-monitor@10 { - compatible =3D "microchip,pac1934"; - reg =3D <0x10>; - - #address-cells =3D <1>; - #size-cells =3D <0>; - - channel@1 { - reg =3D <0x1>; - shunt-resistor-micro-ohms =3D <10000>; - label =3D "VDDREG"; - }; - - channel@2 { - reg =3D <0x2>; - shunt-resistor-micro-ohms =3D <10000>; - label =3D "VDDA25"; - }; - - channel@3 { - reg =3D <0x3>; - shunt-resistor-micro-ohms =3D <10000>; - label =3D "VDD25"; - }; - - channel@4 { - reg =3D <0x4>; - shunt-resistor-micro-ohms =3D <10000>; - label =3D "VDDA_REG"; - }; - }; -}; - -&i2c2 { - status =3D "okay"; -}; - -&mac0 { - phy-mode =3D "sgmii"; - phy-handle =3D <&phy0>; - status =3D "okay"; -}; - -&mac1 { - phy-mode =3D "sgmii"; - phy-handle =3D <&phy1>; - status =3D "okay"; - - phy1: ethernet-phy@9 { - reg =3D <9>; - }; - - phy0: ethernet-phy@8 { - reg =3D <8>; - }; -}; - -&mbox { - status =3D "okay"; -}; - -&mmc { - bus-width =3D <4>; - disable-wp; - cap-sd-highspeed; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - status =3D "okay"; -}; - -&mmuart1 { - status =3D "okay"; -}; - -&mmuart2 { - status =3D "okay"; -}; - -&mmuart3 { - status =3D "okay"; -}; - -&mmuart4 { - status =3D "okay"; -}; - -&pcie { - status =3D "okay"; -}; - -&qspi { - status =3D "okay"; -}; - -&refclk { - clock-frequency =3D <125000000>; -}; - -&refclk_ccc { - clock-frequency =3D <50000000>; -}; - -&rtc { - status =3D "okay"; -}; - -&spi0 { - status =3D "okay"; -}; - -&spi1 { - status =3D "okay"; -}; - -&syscontroller { - status =3D "okay"; -}; - -&syscontroller_qspi { - /* - * The flash *is* there, but Icicle kits that have engineering sample - * silicon (write?) access to this flash to non-functional. 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Engineering samples cannot write to flash from the MSS, as noted in the PolarFire SoC FPGA ES errata. Add specific compatibles for the Icicle Kit with Production device (MPFS250T) and Icicle Kit with Engineering Sample (MPFS250T_ES). The icicle kit reference designs in the v2025.07 release include the Mi-V IHC IP v2, used to send/receive data between clusters when using Asymmetric Multiprocessing (AMP) mode. In reference design releases prior to v2025.07, the MI-V IHC subsystem was included as a proof of concept in the design prior to becoming an IP available in the Libero catalog. Among other improvements, the new Mi-V IHC IP v2 includes some changes to the register map. For this reason, make use of a new reference design compatible to denote that v2025.07 reference design releases are not backwards compatible. Signed-off-by: Valentina Fernandez --- Documentation/devicetree/bindings/riscv/microchip.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Docum= entation/devicetree/bindings/riscv/microchip.yaml index 78ce76ae1b6d..8ddc5c02973e 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -18,10 +18,18 @@ properties: const: '/' compatible: oneOf: + - items: + - const: microchip,mpfs-icicle-prod-reference-rtl-v2507 + - const: microchip,mpfs-icicle-kit-prod + - const: microchip,mpfs-icicle-kit + - const: microchip,mpfs-prod + - const: microchip,mpfs + - items: - enum: - microchip,mpfs-icicle-reference-rtlv2203 - microchip,mpfs-icicle-reference-rtlv2210 + - microchip,mpfs-icicle-es-reference-rtl-v2507 - const: microchip,mpfs-icicle-kit - const: microchip,mpfs =20 --=20 2.34.1 From nobody Wed Sep 10 02:03:22 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E58C42A1D1; Mon, 8 Sep 2025 11:48:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757332137; cv=none; b=qT88Lr/lfO74YDEHWgAWz34j5wvMVWbMgsx8L+RjRMPg3ANTeiO2IdVZYpxWmmcvwpeOORxyqdaaqISjOn8QPtFOh8phA2yaCvNgqiK1BVf4OHLzkEFw8PVvnhSn35Pq2R55vn2Hanqs+nkuMJwm+bCZfux+4o70rieWNB9LlhA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757332137; c=relaxed/simple; bh=khzirs232ONv9Ti/rgyEG1nzqfuQZeNc7eGF+WvAWTw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ScM8sFGvTjyDJhrpM7U34aMCHNFSdUHa8BFQeM0JaPOcJ+XZhkJ3QA92QQ+O+iytS74PsNde55ql02m11oaLbFeMY04/62gw4Sua3MoXTMkTpusR5WIOuUdKnjpmehGsJ2VkDvHPL56dOr8WBJjFIRrX5cGFGX+n2jl0cx590aI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=mF6Myaxr; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="mF6Myaxr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1757332135; x=1788868135; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=khzirs232ONv9Ti/rgyEG1nzqfuQZeNc7eGF+WvAWTw=; b=mF6MyaxrTk8oCibTopOL5D5cKFEBWy7EuyuPEqup8lhGQysM1js2dr5x 4le0oW+h0SXJRwIVwpHXUlXSAEWu3NSdewYkpgy43js/2Ehx1DkUEejqS UGyGJvXVNDZSQBHfU3zOjE0Kd8qJRlJlb79xItfx9bGBjpbcDlLGo40li mU7xa5os7WsuJN3jD3DpNcjps68o2iBnKWGWUSPkpdMR7omGlV2CSbujp ALpmUrRyZskGw1JZWR0JQ8pTuv87da7VO4ExNPHxoAmZVBwDQVxStS4tS Mg2c8yRN8Y1oZm/VI2KcIkBHWxY4bQstXn5iyhmhMHybUOAXZR0CLcd/r A==; X-CSE-ConnectionGUID: vDOPHTnsQiaqmkXt9yltVw== X-CSE-MsgGUID: CFRpFRBqQ0+zmhKj6MR+UA== X-IronPort-AV: E=Sophos;i="6.18,248,1751266800"; d="scan'208";a="45634878" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 08 Sep 2025 04:48:54 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Mon, 8 Sep 2025 04:48:43 -0700 Received: from valentina.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 8 Sep 2025 04:48:40 -0700 From: Valentina Fernandez To: , , , , , , , , CC: , , Subject: [PATCH v3 3/6] riscv: dts: microchip: add icicle kit with production device Date: Mon, 8 Sep 2025 12:57:29 +0100 Message-ID: <20250908115732.31092-4-valentina.fernandezalanis@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908115732.31092-1-valentina.fernandezalanis@microchip.com> References: <20250908115732.31092-1-valentina.fernandezalanis@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With the introduction of the Icicle Kit using the production MPFS250T device, it's necessary to distinguish it from the engineering sample (-es) variant. Engineering samples cannot write to flash from the MSS, as noted in the PolarFire SoC FPGA ES errata. Add a new device tree (mpfs-icicle-kit-prod.dts) for the production board which includes the icicle kit common dtsi and enable the system controller SPI flash, which is only accessible on production silicon. Remove redundant board compatible from fabric dtsi and update board compatibles for v2025.07 release, which includes Mi-V IHC v2 for AMP cluster communication. Signed-off-by: Valentina Fernandez --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-icicle-kit-common.dtsi | 4 ++++ .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 23 ++++++++++++++++--- .../dts/microchip/mpfs-icicle-kit-prod.dts | 23 +++++++++++++++++++ .../boot/dts/microchip/mpfs-icicle-kit.dts | 3 ++- 5 files changed, 50 insertions(+), 4 deletions(-) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/m= icrochip/Makefile index f51aeeb9fd3b..1e2f4e41bf0d 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-beaglev-fire.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-icicle-kit.dtb +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-icicle-kit-prod.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-m100pfsevp.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-polarberry.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-sev-kit.dtb diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi index eafea3b69cd7..5c7a8ffad85b 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi @@ -134,6 +134,10 @@ &i2c2 { status =3D "okay"; }; =20 +&ihc { + status =3D "okay"; +}; + &mac0 { phy-mode =3D "sgmii"; phy-handle =3D <&phy0>; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index a6dda55a2d1d..e673b676fd1a 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -2,9 +2,6 @@ /* Copyright (c) 2020-2021 Microchip Technology Inc */ =20 / { - compatible =3D "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpf= s-icicle-kit", - "microchip,mpfs"; - core_pwm0: pwm@40000000 { compatible =3D "microchip,corepwm-rtl-v4"; reg =3D <0x0 0x40000000 0x0 0xF0>; @@ -26,6 +23,26 @@ i2c2: i2c@40000200 { status =3D "disabled"; }; =20 + ihc: mailbox { + compatible =3D "microchip,sbi-ipc"; + interrupt-parent =3D <&plic>; + interrupts =3D <180>, <179>, <178>, <177>; + interrupt-names =3D "hart-1", "hart-2", "hart-3", "hart-4"; + #mbox-cells =3D <1>; + status =3D "disabled"; + }; + + mailbox@50000000 { + compatible =3D "microchip,miv-ihc-rtl-v2"; + reg =3D <0x0 0x50000000 0x0 0x1c000>; + interrupt-parent =3D <&plic>; + interrupts =3D <180>, <179>, <178>, <177>; + interrupt-names =3D "hart-1", "hart-2", "hart-3", "hart-4"; + #mbox-cells =3D <1>; + microchip,ihc-chan-disabled-mask =3D /bits/ 16 <0>; + status =3D "disabled"; + }; + pcie: pcie@3000000000 { compatible =3D "microchip,pcie-host-1.0"; #address-cells =3D <0x3>; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts b/arch/= riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts new file mode 100644 index 000000000000..8afedece89d1 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2025 Microchip Technology Inc */ + +/dts-v1/; + +#include "mpfs-icicle-kit-common.dtsi" + +/ { + model =3D "Microchip PolarFire-SoC Icicle Kit (Production Silicon)"; + compatible =3D "microchip,mpfs-icicle-prod-reference-rtl-v2507", + "microchip,mpfs-icicle-kit-prod", + "microchip,mpfs-icicle-kit", + "microchip,mpfs-prod", + "microchip,mpfs"; +}; + +&syscontroller { + microchip,bitstream-flash =3D <&sys_ctrl_flash>; +}; + +&syscontroller_qspi { + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv= /boot/dts/microchip/mpfs-icicle-kit.dts index 2cb08ed0946d..556aa9638282 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -7,6 +7,7 @@ =20 / { model =3D "Microchip PolarFire-SoC Icicle Kit"; - compatible =3D "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpf= s-icicle-kit", + compatible =3D "microchip,mpfs-icicle-es-reference-rtl-v2507", + "microchip,mpfs-icicle-kit", "microchip,mpfs"; }; --=20 2.34.1 From nobody Wed Sep 10 02:03:22 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 801CD2ECD3F; Mon, 8 Sep 2025 11:48:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Rename the Clock Conditioning Circuit (CCC) reference clock to match the fixed clock bindings naming recommendation. Update the reserved memory regions in the Icicle Kit common dtsi to use lowercase hex and drop the redundant status properties from the memory regions, as they are not required. Signed-off-by: Valentina Fernandez --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi | 6 ++---- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 2 +- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi index 5c7a8ffad85b..e01a216e6c3a 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi @@ -53,13 +53,11 @@ led-4 { ddrc_cache_lo: memory@80000000 { device_type =3D "memory"; reg =3D <0x0 0x80000000 0x0 0x40000000>; - status =3D "okay"; }; =20 ddrc_cache_hi: memory@1040000000 { device_type =3D "memory"; reg =3D <0x10 0x40000000 0x0 0x40000000>; - status =3D "okay"; }; =20 reserved-memory { @@ -67,8 +65,8 @@ reserved-memory { #size-cells =3D <2>; ranges; =20 - hss_payload: region@BFC00000 { - reg =3D <0x0 0xBFC00000 0x0 0x400000>; + hss_payload: region@bfc00000 { + reg =3D <0x0 0xbfc00000 0x0 0x400000>; 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08 Sep 2025 04:48:55 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Mon, 8 Sep 2025 04:48:48 -0700 Received: from valentina.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 8 Sep 2025 04:48:46 -0700 From: Valentina Fernandez To: , , , , , , , , CC: , , Subject: [PATCH v3 5/6] dt-bindings: riscv: microchip: document Discovery Kit Date: Mon, 8 Sep 2025 12:57:31 +0100 Message-ID: <20250908115732.31092-6-valentina.fernandezalanis@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908115732.31092-1-valentina.fernandezalanis@microchip.com> References: <20250908115732.31092-1-valentina.fernandezalanis@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Discovery Kit (MPFS-DISCO-KIT) is a development board featuring a Microchip PolarFire SoC MPFS095T. Link: https://www.microchip.com/en-us/development-tool/mpfs-disco-kit Signed-off-by: Valentina Fernandez --- Documentation/devicetree/bindings/riscv/microchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Docum= entation/devicetree/bindings/riscv/microchip.yaml index 8ddc5c02973e..381d6eb6672e 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -33,6 +33,11 @@ properties: - const: microchip,mpfs-icicle-kit - const: microchip,mpfs =20 + - items: + - const: microchip,mpfs-disco-kit-reference-rtl-v2507 + - const: microchip,mpfs-disco-kit + - const: microchip,mpfs + - items: - enum: - aldec,tysom-m-mpfs250t-rev2 --=20 2.34.1 From nobody Wed Sep 10 02:03:22 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4DB92FABFE; Mon, 8 Sep 2025 11:48:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757332139; cv=none; b=N6IwOJTfHOkfqdjvyVjvjUXvuNr7xXrCYEYhQG8XJGyEruI6S6JC4dAJroL9HbcUbkk4HnAOqgJgwHklG2+/UzUpGRdUWoa0yK67C/QMKw7YKc6VG1N8RIcljo/OJaooI7nE9afbClkOpm94d2zfjMJqWtS8WjXDT2pJkSilFZk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757332139; c=relaxed/simple; bh=fKTa6YCaaBumc82npv2gUD3y7Mci5DJDAQ4IQFBtl2k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WK2cVFUj3XkMKoPR+Vwz9IfEiKP4IRoWgxZ7zHCzmaJwFRBeNUg8vm32pBLxpSnnhjf4Jbjy259yyXdowkZp/SZIMifTJWHaBVHGqwgBuunNwhtsGXX5RdRwG0SGwuvGDk/aPFsm+QSmFx6MKfwcq52b6OHos80TnHDHSeDBrYA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=HicQmQli; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="HicQmQli" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1757332137; x=1788868137; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fKTa6YCaaBumc82npv2gUD3y7Mci5DJDAQ4IQFBtl2k=; b=HicQmQli78VDvBn0tAleLuUou3qkXf0LbHTGjnM4RXYIzxK4Yvkj1U+v 7m73cIiWicslMV/yyh/g1x2xE3pZGkg+sqo2epk3ACTbcuj7kgdk49Rx4 IL8BA5YT1Qb9mY5u/EVYAUMltgqGAo8ivlhZdzPW18qfS61wqnEQJ7KNT 9DUukP7mBW4M3AqMn0U/AW9YCW+YDzY0+izv/zw7GC3inQEvDW6t2teEn StVQCd/Ia+lov/ZZUWIhy63Rt8q8gVEVrU/bgBjA+rFvdIqRUdanZ44++ FBoENnQPuYsrs6ZFHDu8ywUjKwhNBC5XoOWWFH4jj59/iMH82al93WYK9 Q==; X-CSE-ConnectionGUID: vDOPHTnsQiaqmkXt9yltVw== X-CSE-MsgGUID: 1LiFos11Rp2I2DFuSCaZqA== X-IronPort-AV: E=Sophos;i="6.18,248,1751266800"; d="scan'208";a="45634882" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 08 Sep 2025 04:48:55 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Mon, 8 Sep 2025 04:48:51 -0700 Received: from valentina.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 8 Sep 2025 04:48:48 -0700 From: Valentina Fernandez To: , , , , , , , , CC: , , Subject: [PATCH v3 6/6] riscv: dts: microchip: add a device tree for Discovery Kit Date: Mon, 8 Sep 2025 12:57:32 +0100 Message-ID: <20250908115732.31092-7-valentina.fernandezalanis@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908115732.31092-1-valentina.fernandezalanis@microchip.com> References: <20250908115732.31092-1-valentina.fernandezalanis@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a minimal device tree for the Microchip PolarFire SoC Discovery Kit. The Discovery Kit is a cost-optimized board based on PolarFire SoC MPFS095T and features: - 1 GB DDR4x16 - 1x Gigabit Ethernet - 3x UARTs - Raspberry Pi connector - mikroBus connector - microSD card connector Link: https://www.microchip.com/en-us/development-tool/mpfs-disco-kit Signed-off-by: Valentina Fernandez --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-disco-kit-fabric.dtsi | 58 ++++++ .../boot/dts/microchip/mpfs-disco-kit.dts | 190 ++++++++++++++++++ 3 files changed, 249 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/m= icrochip/Makefile index 1e2f4e41bf0d..345ed7a48cc1 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-beaglev-fire.dtb +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-disco-kit.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-icicle-kit.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-icicle-kit-prod.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-m100pfsevp.dtb diff --git a/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi b/arc= h/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi new file mode 100644 index 000000000000..ae8be7d6f392 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2025 Microchip Technology Inc */ + +/ { + core_pwm0: pwm@40000000 { + compatible =3D "microchip,corepwm-rtl-v4"; + reg =3D <0x0 0x40000000 0x0 0xF0>; + microchip,sync-update-mask =3D /bits/ 32 <0>; + #pwm-cells =3D <3>; + clocks =3D <&ccc_sw CLK_CCC_PLL0_OUT3>; + status =3D "disabled"; + }; + + i2c2: i2c@40000200 { + compatible =3D "microchip,corei2c-rtl-v7"; + reg =3D <0x0 0x40000200 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&ccc_sw CLK_CCC_PLL0_OUT3>; + interrupt-parent =3D <&plic>; + interrupts =3D <122>; + clock-frequency =3D <100000>; + status =3D "disabled"; + }; + + ihc: mailbox { + compatible =3D "microchip,sbi-ipc"; + interrupt-parent =3D <&plic>; + interrupts =3D <180>, <179>, <178>, <177>; + interrupt-names =3D "hart-1", "hart-2", "hart-3", "hart-4"; + #mbox-cells =3D <1>; + status =3D "disabled"; + }; + + mailbox@50000000 { + compatible =3D "microchip,miv-ihc-rtl-v2"; + reg =3D <0x0 0x50000000 0x0 0x1c000>; + interrupt-parent =3D <&plic>; + interrupts =3D <180>, <179>, <178>, <177>; + interrupt-names =3D "hart-1", "hart-2", "hart-3", "hart-4"; + #mbox-cells =3D <1>; + microchip,ihc-chan-disabled-mask =3D /bits/ 16 <0>; + status =3D "disabled"; + }; + + refclk_ccc: clock-cccref { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; +}; + +&ccc_sw { + clocks =3D <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, + <&refclk_ccc>, <&refclk_ccc>; + clock-names =3D "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", + "dll0_ref", "dll1_ref"; + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts b/arch/riscv/= boot/dts/microchip/mpfs-disco-kit.dts new file mode 100644 index 000000000000..c068b9bb5bfd --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2025 Microchip Technology Inc */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-disco-kit-fabric.dtsi" +#include +#include + +/ { + model =3D "Microchip PolarFire-SoC Discovery Kit"; + compatible =3D "microchip,mpfs-disco-kit-reference-rtl-v2507", + "microchip,mpfs-disco-kit", + "microchip,mpfs"; + + aliases { + ethernet0 =3D &mac0; + serial4 =3D &mmuart4; + }; + + chosen { + stdout-path =3D "serial4:115200n8"; + }; + + leds { + compatible =3D "gpio-leds"; + + led-1 { + gpios =3D <&gpio2 17 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led1"; + }; + + led-2 { + gpios =3D <&gpio2 18 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led2"; + }; + + led-3 { + gpios =3D <&gpio2 19 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led3"; + }; + + led-4 { + gpios =3D <&gpio2 20 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led4"; + }; + + led-5 { + gpios =3D <&gpio2 21 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led5"; + }; + + led-6 { + gpios =3D <&gpio2 22 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led6"; + }; + + led-7 { + gpios =3D <&gpio2 23 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led7"; + }; + + led-8 { + gpios =3D <&gpio1 9 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led8"; + }; + }; + + ddrc_cache_lo: memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x40000000>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + hss_payload: region@bfc00000 { + reg =3D <0x0 0xbfc00000 0x0 0x400000>; + no-map; + }; + }; +}; + +&core_pwm0 { + status =3D "okay"; +}; + +&gpio1 { + interrupts =3D <27>, <28>, <29>, <30>, + <31>, <32>, <33>, <47>, + <35>, <36>, <37>, <38>, + <39>, <40>, <41>, <42>, + <43>, <44>, <45>, <46>, + <47>, <48>, <49>, <50>; + status =3D "okay"; +}; + +&gpio2 { + interrupts =3D <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; +}; + +&i2c2 { + status =3D "okay"; +}; + +&ihc { + status =3D "okay"; +}; + +&mac0 { + phy-mode =3D "sgmii"; + phy-handle =3D <&phy0>; + status =3D "okay"; + + phy0: ethernet-phy@b { + reg =3D <0xb>; + }; +}; + +&mbox { + status =3D "okay"; +}; + +&mmc { + bus-width =3D <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + no-1-8-v; + status =3D "okay"; +}; + +&mmuart1 { + status =3D "okay"; +}; + +&mmuart4 { + status =3D "okay"; +}; + +&refclk { + clock-frequency =3D <125000000>; +}; + +&refclk_ccc { + clock-frequency =3D <50000000>; +}; + +&rtc { + status =3D "okay"; +}; + +&spi0 { + status =3D "okay"; +}; + +&spi1 { + status =3D "okay"; +}; + +&syscontroller { + status =3D "okay"; +}; --=20 2.34.1