The s32g2 and s32g3 NXP platforms have two instances of a Successive
Approximation Register ADC. It supports the raw, trigger and scan
modes which involves the DMA. Add their descriptions.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
 .../bindings/iio/adc/nxp,s32g2-sar-adc.yaml   | 68 +++++++++++++++++++
 1 file changed, 68 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/iio/adc/nxp,s32g2-sar-adc.yaml

diff --git a/Documentation/devicetree/bindings/iio/adc/nxp,s32g2-sar-adc.yaml b/Documentation/devicetree/bindings/iio/adc/nxp,s32g2-sar-adc.yaml
new file mode 100644
index 000000000000..dc6ec240f816
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/nxp,s32g2-sar-adc.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/nxp,s32g2-sar-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP Successive Approximation ADC
+
+description:
+  The NXP SAR ADC provides fast and accurate analog-to-digital
+  conversion using the Successive Approximation Register (SAR) method.
+  It has 12-bit resolution with 8 input channels. Conversions can be
+  launched in software or using hardware triggers. It supports
+  continuous and one-shot modes with separate registers.
+
+maintainers:
+  - Daniel Lezcano <daniel.lezcano@kernel.org>
+
+properties:
+  compatible:
+    oneOf:
+      - const: nxp,s32g2-sar-adc
+      - items:
+          - const: nxp,s32g3-sar-adc
+          - const: nxp,s32g2-sar-adc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+
+  clock-names:
+    minItems: 1
+
+  dmas:
+    minItems: 1
+
+  dma-names:
+    const: rx
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - dmas
+  - dma-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    adc@401f8000 {
+        compatible = "nxp,s32g2-sar-adc";
+        reg = <0x401f8000 0x1000>;
+        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clks 0x41>;
+        clock-names = "adc";
+        dmas = <&edma0 0 32>;
+        dma-names = "rx";
+    };
-- 
2.43.0

On 03/09/2025 12:27, Daniel Lezcano wrote:
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - const: nxp,s32g2-sar-adc
> +      - items:
> +          - const: nxp,s32g3-sar-adc
> +          - const: nxp,s32g2-sar-adc
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    minItems: 1

Wrong constraint, look at other properties here. maxItems

> +
> +  clock-names:
> +    minItems: 1

Missing constraints, just drop entire clock-names.

> +
> +  dmas:
> +    minItems: 1

Also needs fixes.

> +
> +  dma-names:
> +    const: rx
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +  - dmas
> +  - dma-names



Best regards,
Krzysztof

On 9/3/25 5:27 AM, Daniel Lezcano wrote:

...

> +  clock-names:
> +    minItems: 1

Usually if there is only 1 clock, we don't bother with clock-names.

If we keep clock names though, I think it should be:

  clock-names:
    items:
      const: adc

Since that is the only allowed name.

Although the reference manual calls this the "bus" clock, so that might be a
better name.

> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    adc@401f8000 {
> +        compatible = "nxp,s32g2-sar-adc";
> +        reg = <0x401f8000 0x1000>;
> +        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&clks 0x41>;
> +        clock-names = "adc";
> +        dmas = <&edma0 0 32>;
> +        dma-names = "rx";
> +    };

On Wed, 03 Sep 2025 12:27:55 +0200, Daniel Lezcano wrote:
> The s32g2 and s32g3 NXP platforms have two instances of a Successive
> Approximation Register ADC. It supports the raw, trigger and scan
> modes which involves the DMA. Add their descriptions.
> 
> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> ---
>  .../bindings/iio/adc/nxp,s32g2-sar-adc.yaml   | 68 +++++++++++++++++++
>  1 file changed, 68 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/iio/adc/nxp,s32g2-sar-adc.yaml
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>