Il 27/08/25 13:37, Jason-JH Lin ha scritto:
> To support hardware without subsys IDs on new SoCs, add a programming
> flow that checks whether the subsys ID is valid.
>
> If the subsys ID is valid, the flow will call cmdq_pkt_write_subsys()
> instead of the original cmdq_pkt_write().
>
> If the subsys ID is invalid, the flow will call cmdq_pkt_write_mask_pa()
> to achieve the same functionality.
>
> Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com>
In mediatek-drm and in mtk-mdp3 the performance of mtk_ddp_write is important: in
both, there are ways to know whether a platform is expected to always use the
cmdq_pkt_write_mask_pa() or the subsys() one.
Please check what platform is this driver running on - based on the platform, you
can assign a function pointer, so that you always call it like
priv->write_cmdq_pkt(cmdq_pkt, cmdq_reg, ofst, val, mask);
write_cmdq_pkt() could point to, either:
1. A function that checks if subsys != CMDQ_SUBSYS_INVALID, for platforms that
are expected to have mixed PA *and* SUBSYS (hopefully none!!!); or
2. The cmdq_pkt_write_mask_subsys() function; or
3. The cmdq_pkt_write_mask_pa() function.
This removes lots and lots of branches at every call.
I want to remind you that CMDQ packets are being generated in many cases in the
mediatek-drm driver, one of which is upon VBLANK; Think of the case in which we
are driving a high refresh rate display (>=120Hz): not just in DSI Video mode
for which we manage just only vblanks and data pumping (which still needs quite
a bit of GCE writes).. but something like DSI CMD mode would probably generate
*a myriad* of GCE calls.... and that is only one of the cases, there are more
that don't involve specifically DSI.
Of course, for mtk-mdp3 there's a different story - but I guess it's useless to
add a specific example for that, I'm sure you got the point here.
Cheers,
Angelo
> ---
> drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24 ++++++++++++++++++------
> 1 file changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> index ac6620e10262..d902a65e1232 100644
> --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> @@ -66,14 +66,28 @@ struct mtk_ddp_comp_dev {
> struct cmdq_client_reg cmdq_reg;
> };
>
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> +static int mtk_ddp_write_cmdq_pkt(struct cmdq_pkt *cmdq_pkt, struct cmdq_client_reg *cmdq_reg,
> + unsigned int offset, unsigned int value, unsigned int mask)
> +{
> + offset += cmdq_reg->offset;
> +
> + if (cmdq_reg->subsys != CMDQ_SUBSYS_INVALID)
> + return cmdq_pkt_write_mask_subsys(cmdq_pkt, cmdq_reg->subsys, cmdq_reg->pa_base,
> + offset, value, mask);
> + else /* only MMIO access, no need to check mminfro_offset */
> + return cmdq_pkt_write_mask_pa(cmdq_pkt, cmdq_reg->subsys, cmdq_reg->pa_base,
> + offset, value, mask);
> +}
> +#endif
> +
> void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
> struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
> unsigned int offset)
> {
> #if IS_REACHABLE(CONFIG_MTK_CMDQ)
> if (cmdq_pkt)
> - cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
> - cmdq_reg->offset + offset, value);
> + mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, GENMASK(31, 0));
> else
> #endif
> writel(value, regs + offset);
> @@ -85,8 +99,7 @@ void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
> {
> #if IS_REACHABLE(CONFIG_MTK_CMDQ)
> if (cmdq_pkt)
> - cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
> - cmdq_reg->offset + offset, value);
> + mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, GENMASK(31, 0));
> else
> #endif
> writel_relaxed(value, regs + offset);
> @@ -98,8 +111,7 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
> {
> #if IS_REACHABLE(CONFIG_MTK_CMDQ)
> if (cmdq_pkt) {
> - cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys,
> - cmdq_reg->offset + offset, value, mask);
> + mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, mask);
> } else {
> #endif
> u32 tmp = readl(regs + offset);