From nobody Wed Oct 1 20:33:19 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FABC312816; Wed, 27 Aug 2025 11:40:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756294825; cv=none; b=Jf3fMtL6GYtA7WQOaKjSrlDE1lpEjNcG1LoNhSosazDJaTkkj/+4bNm782y8wiO57MaoG3FGh5FD8MnRqIFz76kTfa7qSYytoWdDBJkZ6OBNU33i5IcU7OPUhwUvI+C278MqXfBmulUPYPf1mPsexKHlPixoGjLqyCKQPpoAO6k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756294825; c=relaxed/simple; bh=cc3272uJI2nwKm5AyTPofTY1iNMG/ze9CwL2IRJp/J4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MZLXf0F6SiC6MgmfVBIOf5XMdC/uBlhkpAnri+zVaTnwnAyzEqDm9dt3OoPd6Sj2+ZTkVdIiZrcMljQY3FY7+EwkRW3vr5+lknNYoJDRGXSgYRuVNNGeteZS4s/Pli4xJK0k4TbiBD1/GtnXu0w6VVZ/wHOsL7rgyHPVcAxnbBQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=jZ9sSIQY; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="jZ9sSIQY" X-UUID: 9756297a833a11f0bd5779446731db89-20250827 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=/CoNhOf+hJVV4Y8EhRNWJcjEhIvo+2fMZxmyi0epuFI=; b=jZ9sSIQY6FYewEOnjTI257OeLe6Ikvs4jj068phbQ6nM0HXK5UH2t+Q6UUuAvCgySYu1cdVyJekp26iRZq9n/LzcbzBR2yElA8dsn0HxQms5btgXG37ibXp2ppuYp2ZjR4eHIAg5jgqng/uZlsZh4f0cUCJ+gaTe9sehDBNZUnU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.3,REQID:e7b5150f-9491-4d2a-93da-866d7237b6e7,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:f1326cf,CLOUDID:daa59020-786d-4870-a017-e7b4f3839b3f,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:-5,Content:0|15|50,EDM: -3,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0, AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 9756297a833a11f0bd5779446731db89-20250827 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1032027038; Wed, 27 Aug 2025 19:40:11 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Wed, 27 Aug 2025 19:40:10 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Wed, 27 Aug 2025 19:40:09 +0800 From: Jason-JH Lin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jassi Brar , Chun-Kuang Hu , AngeloGioacchino Del Regno , Mauro Carvalho Chehab CC: Matthias Brugger , Nicolas Dufresne , Jason-JH Lin , Nancy Lin , Singo Chang , Paul-PL Chen , Moudy Ho , Xiandong Wang , Sirius Wang , Fei Shao , Chen-yu Tsai , , , , , , , Subject: [PATCH v7 13/20] drm/mediatek: Add programming flow for unsupported subsys ID hardware Date: Wed, 27 Aug 2025 19:37:45 +0800 Message-ID: <20250827114006.3310175-14-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250827114006.3310175-1-jason-jh.lin@mediatek.com> References: <20250827114006.3310175-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" To support hardware without subsys IDs on new SoCs, add a programming flow that checks whether the subsys ID is valid. If the subsys ID is valid, the flow will call cmdq_pkt_write_subsys() instead of the original cmdq_pkt_write(). If the subsys ID is invalid, the flow will call cmdq_pkt_write_mask_pa() to achieve the same functionality. Signed-off-by: Jason-JH Lin --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index ac6620e10262..d902a65e1232 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -66,14 +66,28 @@ struct mtk_ddp_comp_dev { struct cmdq_client_reg cmdq_reg; }; =20 +#if IS_REACHABLE(CONFIG_MTK_CMDQ) +static int mtk_ddp_write_cmdq_pkt(struct cmdq_pkt *cmdq_pkt, struct cmdq_c= lient_reg *cmdq_reg, + unsigned int offset, unsigned int value, unsigned int mask) +{ + offset +=3D cmdq_reg->offset; + + if (cmdq_reg->subsys !=3D CMDQ_SUBSYS_INVALID) + return cmdq_pkt_write_mask_subsys(cmdq_pkt, cmdq_reg->subsys, cmdq_reg->= pa_base, + offset, value, mask); + else /* only MMIO access, no need to check mminfro_offset */ + return cmdq_pkt_write_mask_pa(cmdq_pkt, cmdq_reg->subsys, cmdq_reg->pa_b= ase, + offset, value, mask); +} +#endif + void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, struct cmdq_client_reg *cmdq_reg, void __iomem *regs, unsigned int offset) { #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (cmdq_pkt) - cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, - cmdq_reg->offset + offset, value); + mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, GENMASK(31, 0)= ); else #endif writel(value, regs + offset); @@ -85,8 +99,7 @@ void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, uns= igned int value, { #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (cmdq_pkt) - cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, - cmdq_reg->offset + offset, value); + mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, GENMASK(31, 0)= ); else #endif writel_relaxed(value, regs + offset); @@ -98,8 +111,7 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsig= ned int value, { #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (cmdq_pkt) { - cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys, - cmdq_reg->offset + offset, value, mask); + mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, mask); } else { #endif u32 tmp =3D readl(regs + offset); --=20 2.43.0