arch/arm/boot/dts/nvidia/tegra114.dtsi | 33 +++++ drivers/clk/tegra/Kconfig | 2 +- drivers/clk/tegra/clk-tegra114.c | 30 +++- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 158 +++++++++++++++++---- drivers/clk/tegra/clk.h | 2 - include/dt-bindings/reset/tegra114-car.h | 13 ++ 6 files changed, 204 insertions(+), 34 deletions(-) create mode 100644 include/dt-bindings/reset/tegra114-car.h
DFLL is a dedicated clock source for the Fast CPU. The DFLL is based on a ring oscillator and translates voltage changes into frequency compensation changes needed to prevent the CPU from failing and is essential for correct CPU frequency scaling. --- Changes in v2: - dropped 'drivers:' from commit title - aligned naming to Tegra114 Changes in v3: - add DFLL support for Tegra 114 was split into dt header addition, DFLL reset configuration and CVB tables implementation. - added cleaner commit message to dt header commit - added T210_ prefixes to Tegra210 CVB table macros --- Svyatoslav Ryhel (4): dt-bindings: reset: add Tegra114 car header clk: tegra: add DFLL DVCO reset control for Tegra114 clk: tegra: dfll: add CVB tables for Tegra114 ARM: tegra: Add DFLL clock support for Tegra114 arch/arm/boot/dts/nvidia/tegra114.dtsi | 33 +++++ drivers/clk/tegra/Kconfig | 2 +- drivers/clk/tegra/clk-tegra114.c | 30 +++- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 158 +++++++++++++++++---- drivers/clk/tegra/clk.h | 2 - include/dt-bindings/reset/tegra114-car.h | 13 ++ 6 files changed, 204 insertions(+), 34 deletions(-) create mode 100644 include/dt-bindings/reset/tegra114-car.h -- 2.48.1
On Tue, 26 Aug 2025 09:11:13 +0300, Svyatoslav Ryhel wrote:
> DFLL is a dedicated clock source for the Fast CPU. The DFLL is based on
> a ring oscillator and translates voltage changes into frequency
> compensation changes needed to prevent the CPU from failing and is
> essential for correct CPU frequency scaling.
>
> ---
> Changes in v2:
> - dropped 'drivers:' from commit title
> - aligned naming to Tegra114
>
> Changes in v3:
> - add DFLL support for Tegra 114 was split into dt header addition,
> DFLL reset configuration and CVB tables implementation.
> - added cleaner commit message to dt header commit
> - added T210_ prefixes to Tegra210 CVB table macros
> ---
>
> Svyatoslav Ryhel (4):
> dt-bindings: reset: add Tegra114 car header
> clk: tegra: add DFLL DVCO reset control for Tegra114
> clk: tegra: dfll: add CVB tables for Tegra114
> ARM: tegra: Add DFLL clock support for Tegra114
>
> arch/arm/boot/dts/nvidia/tegra114.dtsi | 33 +++++
> drivers/clk/tegra/Kconfig | 2 +-
> drivers/clk/tegra/clk-tegra114.c | 30 +++-
> drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 158 +++++++++++++++++----
> drivers/clk/tegra/clk.h | 2 -
> include/dt-bindings/reset/tegra114-car.h | 13 ++
> 6 files changed, 204 insertions(+), 34 deletions(-)
> create mode 100644 include/dt-bindings/reset/tegra114-car.h
>
> --
> 2.48.1
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
This patch series was applied (using b4) to base:
Base: attempting to guess base-commit...
Base: tags/next-20250825 (best guess, 3/5 blobs matched)
If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)
New warnings running 'make CHECK_DTBS=y for arch/arm/boot/dts/nvidia/' for 20250826061117.63643-1-clamor95@gmail.com:
arch/arm/boot/dts/nvidia/tegra114-tn7.dtb: /clock@70110000: failed to match any schema with compatible: ['nvidia,tegra114-dfll']
arch/arm/boot/dts/nvidia/tegra114-tn7.dtb: cpu@0 (arm,cortex-a15): 'operating-points' is a dependency of 'clock-latency'
from schema $id: http://devicetree.org/schemas/arm/cpus.yaml#
arch/arm/boot/dts/nvidia/tegra114-tn7.dtb: cpu@0 (arm,cortex-a15): Unevaluated properties are not allowed ('clock-latency' was unexpected)
from schema $id: http://devicetree.org/schemas/arm/cpus.yaml#
arch/arm/boot/dts/nvidia/tegra114-roth.dtb: /clock@70110000: failed to match any schema with compatible: ['nvidia,tegra114-dfll']
arch/arm/boot/dts/nvidia/tegra114-roth.dtb: cpu@0 (arm,cortex-a15): 'operating-points' is a dependency of 'clock-latency'
from schema $id: http://devicetree.org/schemas/arm/cpus.yaml#
arch/arm/boot/dts/nvidia/tegra114-roth.dtb: cpu@0 (arm,cortex-a15): Unevaluated properties are not allowed ('clock-latency' was unexpected)
from schema $id: http://devicetree.org/schemas/arm/cpus.yaml#
arch/arm/boot/dts/nvidia/tegra114-dalmore.dtb: /clock@70110000: failed to match any schema with compatible: ['nvidia,tegra114-dfll']
arch/arm/boot/dts/nvidia/tegra114-dalmore.dtb: cpu@0 (arm,cortex-a15): 'operating-points' is a dependency of 'clock-latency'
from schema $id: http://devicetree.org/schemas/arm/cpus.yaml#
arch/arm/boot/dts/nvidia/tegra114-dalmore.dtb: cpu@0 (arm,cortex-a15): Unevaluated properties are not allowed ('clock-latency' was unexpected)
from schema $id: http://devicetree.org/schemas/arm/cpus.yaml#
arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dtb: /clock@70110000: failed to match any schema with compatible: ['nvidia,tegra114-dfll']
arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dtb: cpu@0 (arm,cortex-a15): 'operating-points' is a dependency of 'clock-latency'
from schema $id: http://devicetree.org/schemas/arm/cpus.yaml#
arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dtb: cpu@0 (arm,cortex-a15): Unevaluated properties are not allowed ('clock-latency' was unexpected)
from schema $id: http://devicetree.org/schemas/arm/cpus.yaml#
On Tuesday, August 26, 2025 3:11 PM Svyatoslav Ryhel wrote: > DFLL is a dedicated clock source for the Fast CPU. The DFLL is based on > a ring oscillator and translates voltage changes into frequency > compensation changes needed to prevent the CPU from failing and is > essential for correct CPU frequency scaling. > > --- > Changes in v2: > - dropped 'drivers:' from commit title > - aligned naming to Tegra114 > > Changes in v3: > - add DFLL support for Tegra 114 was split into dt header addition, > DFLL reset configuration and CVB tables implementation. > - added cleaner commit message to dt header commit > - added T210_ prefixes to Tegra210 CVB table macros > --- > > Svyatoslav Ryhel (4): > dt-bindings: reset: add Tegra114 car header > clk: tegra: add DFLL DVCO reset control for Tegra114 > clk: tegra: dfll: add CVB tables for Tegra114 > ARM: tegra: Add DFLL clock support for Tegra114 > > arch/arm/boot/dts/nvidia/tegra114.dtsi | 33 +++++ > drivers/clk/tegra/Kconfig | 2 +- > drivers/clk/tegra/clk-tegra114.c | 30 +++- > drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 158 +++++++++++++++++---- > drivers/clk/tegra/clk.h | 2 - > include/dt-bindings/reset/tegra114-car.h | 13 ++ > 6 files changed, 204 insertions(+), 34 deletions(-) > create mode 100644 include/dt-bindings/reset/tegra114-car.h Whole series, Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
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