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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afe492da4b9sm711067966b.63.2025.08.25.23.11.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Aug 2025 23:11:41 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd , "Rafael J. Wysocki" , Viresh Kumar , Philipp Zabel , Svyatoslav Ryhel Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 1/4] dt-bindings: reset: add Tegra114 car header Date: Tue, 26 Aug 2025 09:11:14 +0300 Message-ID: <20250826061117.63643-2-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250826061117.63643-1-clamor95@gmail.com> References: <20250826061117.63643-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Binding values for special resets that are placed starting from software-defined index 160 in line with other chips. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- include/dt-bindings/reset/tegra114-car.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 include/dt-bindings/reset/tegra114-car.h diff --git a/include/dt-bindings/reset/tegra114-car.h b/include/dt-bindings= /reset/tegra114-car.h new file mode 100644 index 000000000000..d7908d810ddf --- /dev/null +++ b/include/dt-bindings/reset/tegra114-car.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * This header provides Tegra114-specific constants for binding + * nvidia,tegra114-car. + */ + +#ifndef _DT_BINDINGS_RESET_TEGRA114_CAR_H +#define _DT_BINDINGS_RESET_TEGRA114_CAR_H + +#define TEGRA114_RESET(x) (5 * 32 + (x)) +#define TEGRA114_RST_DFLL_DVCO TEGRA114_RESET(0) + +#endif /* _DT_BINDINGS_RESET_TEGRA114_CAR_H */ --=20 2.48.1 From nobody Fri Oct 3 19:11:40 2025 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 650792F532C; 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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afe492da4b9sm711067966b.63.2025.08.25.23.11.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Aug 2025 23:11:43 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd , "Rafael J. Wysocki" , Viresh Kumar , Philipp Zabel , Svyatoslav Ryhel Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 2/4] clk: tegra: add DFLL DVCO reset control for Tegra114 Date: Tue, 26 Aug 2025 09:11:15 +0300 Message-ID: <20250826061117.63643-3-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250826061117.63643-1-clamor95@gmail.com> References: <20250826061117.63643-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The DVCO present in the DFLL IP block has a separate reset line, exposed via the CAR IP block. This reset line is asserted upon SoC reset. Unless something (such as the DFLL driver) deasserts this line, the DVCO will not oscillate, although reads and writes to the DFLL IP block will complete. Based on a3c83ff2 ("clk: tegra: Add DFLL DVCO reset control for Tegra124") Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- drivers/clk/tegra/clk-tegra114.c | 30 ++++++++++++++++++++++++++---- drivers/clk/tegra/clk.h | 2 -- 2 files changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra= 114.c index 186b0b81c1ec..3eaa97c7d79e 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -11,6 +11,7 @@ #include #include #include +#include =20 #include "clk.h" #include "clk-id.h" @@ -1274,7 +1275,7 @@ EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init); * * Assert the reset line of the DFLL's DVCO. No return value. */ -void tegra114_clock_assert_dfll_dvco_reset(void) +static void tegra114_clock_assert_dfll_dvco_reset(void) { u32 v; =20 @@ -1283,7 +1284,6 @@ void tegra114_clock_assert_dfll_dvco_reset(void) writel_relaxed(v, clk_base + RST_DFLL_DVCO); tegra114_car_barrier(); } -EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset); =20 /** * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset @@ -1291,7 +1291,7 @@ EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset); * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to * operate. No return value. */ -void tegra114_clock_deassert_dfll_dvco_reset(void) +static void tegra114_clock_deassert_dfll_dvco_reset(void) { u32 v; =20 @@ -1300,7 +1300,26 @@ void tegra114_clock_deassert_dfll_dvco_reset(void) writel_relaxed(v, clk_base + RST_DFLL_DVCO); tegra114_car_barrier(); } -EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset); + +static int tegra114_reset_assert(unsigned long id) +{ + if (id =3D=3D TEGRA114_RST_DFLL_DVCO) + tegra114_clock_assert_dfll_dvco_reset(); + else + return -EINVAL; + + return 0; +} + +static int tegra114_reset_deassert(unsigned long id) +{ + if (id =3D=3D TEGRA114_RST_DFLL_DVCO) + tegra114_clock_deassert_dfll_dvco_reset(); + else + return -EINVAL; + + return 0; +} =20 static void __init tegra114_clock_init(struct device_node *np) { @@ -1346,6 +1365,9 @@ static void __init tegra114_clock_init(struct device_= node *np) tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks, &pll_x_params); =20 + tegra_init_special_resets(1, tegra114_reset_assert, + tegra114_reset_deassert); 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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afe492da4b9sm711067966b.63.2025.08.25.23.11.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Aug 2025 23:11:44 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd , "Rafael J. Wysocki" , Viresh Kumar , Philipp Zabel , Svyatoslav Ryhel Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 3/4] clk: tegra: dfll: add CVB tables for Tegra114 Date: Tue, 26 Aug 2025 09:11:16 +0300 Message-ID: <20250826061117.63643-4-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250826061117.63643-1-clamor95@gmail.com> References: <20250826061117.63643-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the Tegra124 DFLL driver to include configuration settings required for Tegra114 compatibility. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- drivers/clk/tegra/Kconfig | 2 +- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 158 +++++++++++++++++---- 2 files changed, 132 insertions(+), 28 deletions(-) diff --git a/drivers/clk/tegra/Kconfig b/drivers/clk/tegra/Kconfig index 90df619dc087..62147a069606 100644 --- a/drivers/clk/tegra/Kconfig +++ b/drivers/clk/tegra/Kconfig @@ -4,7 +4,7 @@ config CLK_TEGRA_BPMP depends on TEGRA_BPMP =20 config TEGRA_CLK_DFLL - depends on ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC + depends on ARCH_TEGRA_114_SOC || ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC select PM_OPP def_bool y =20 diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra= /clk-tegra124-dfll-fcpu.c index 0251618b82c8..1405217fed5d 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -28,6 +28,99 @@ struct dfll_fcpu_data { unsigned int cpu_cvb_tables_size; }; =20 +/* Maximum CPU frequency, indexed by CPU speedo id */ +static const unsigned long tegra114_cpu_max_freq_table[] =3D { + [0] =3D 2040000000UL, + [1] =3D 1810500000UL, + [2] =3D 1912500000UL, + [3] =3D 1810500000UL, +}; + +#define T114_CPU_CVB_TABLE \ + .min_millivolts =3D 1000, \ + .max_millivolts =3D 1320, \ + .speedo_scale =3D 100, \ + .voltage_scale =3D 1000, \ + .entries =3D { \ + { 306000000UL, { 2190643, -141851, 3576 } }, \ + { 408000000UL, { 2250968, -144331, 3576 } }, \ + { 510000000UL, { 2313333, -146811, 3576 } }, \ + { 612000000UL, { 2377738, -149291, 3576 } }, \ + { 714000000UL, { 2444183, -151771, 3576 } }, \ + { 816000000UL, { 2512669, -154251, 3576 } }, \ + { 918000000UL, { 2583194, -156731, 3576 } }, \ + { 1020000000UL, { 2655759, -159211, 3576 } }, \ + { 1122000000UL, { 2730365, -161691, 3576 } }, \ + { 1224000000UL, { 2807010, -164171, 3576 } }, \ + { 1326000000UL, { 2885696, -166651, 3576 } }, \ + { 1428000000UL, { 2966422, -169131, 3576 } }, \ + { 1530000000UL, { 3049183, -171601, 3576 } }, \ + { 1606500000UL, { 3112179, -173451, 3576 } }, \ + { 1708500000UL, { 3198504, -175931, 3576 } }, \ + { 1810500000UL, { 3304747, -179126, 3576 } }, \ + { 1912500000UL, { 3395401, -181606, 3576 } }, \ + { 0UL, { 0, 0, 0 } }, \ + }, \ + .cpu_dfll_data =3D { \ + .tune0_low =3D 0x00b0039d, \ + .tune0_high =3D 0x00b0009d, \ + .tune1 =3D 0x0000001f, \ + .tune_high_min_millivolts =3D 1050, \ + } + +static const struct cvb_table tegra114_cpu_cvb_tables[] =3D { + { + .speedo_id =3D 0, + .process_id =3D -1, + .min_millivolts =3D 1000, + .max_millivolts =3D 1250, + .speedo_scale =3D 100, + .voltage_scale =3D 100, + .entries =3D { + { 306000000UL, { 107330, -1569, 0 } }, + { 408000000UL, { 111250, -1666, 0 } }, + { 510000000UL, { 110000, -1460, 0 } }, + { 612000000UL, { 117290, -1745, 0 } }, + { 714000000UL, { 122700, -1910, 0 } }, + { 816000000UL, { 125620, -1945, 0 } }, + { 918000000UL, { 130560, -2076, 0 } }, + { 1020000000UL, { 137280, -2303, 0 } }, + { 1122000000UL, { 146440, -2660, 0 } }, + { 1224000000UL, { 152190, -2825, 0 } }, + { 1326000000UL, { 157520, -2953, 0 } }, + { 1428000000UL, { 166100, -3261, 0 } }, + { 1530000000UL, { 176410, -3647, 0 } }, + { 1632000000UL, { 189620, -4186, 0 } }, + { 1734000000UL, { 203190, -4725, 0 } }, + { 1836000000UL, { 222670, -5573, 0 } }, + { 1938000000UL, { 256210, -7165, 0 } }, + { 2040000000UL, { 250050, -6544, 0 } }, + { 0UL, { 0, 0, 0 } }, + }, + .cpu_dfll_data =3D { + .tune0_low =3D 0x00b0019d, + .tune0_high =3D 0x00b0019d, + .tune1 =3D 0x0000001f, + .tune_high_min_millivolts =3D 1000, + } + }, + { + .speedo_id =3D 1, + .process_id =3D -1, + T114_CPU_CVB_TABLE + }, + { + .speedo_id =3D 2, + .process_id =3D -1, + T114_CPU_CVB_TABLE + }, + { + .speedo_id =3D 3, + .process_id =3D -1, + T114_CPU_CVB_TABLE + }, +}; + /* Maximum CPU frequency, indexed by CPU speedo id */ static const unsigned long tegra124_cpu_max_freq_table[] =3D { [0] =3D 2014500000UL, @@ -93,7 +186,7 @@ static const unsigned long tegra210_cpu_max_freq_table[]= =3D { [10] =3D 1504500000UL, }; =20 -#define CPU_CVB_TABLE \ +#define T210_CPU_CVB_TABLE \ .speedo_scale =3D 100, \ .voltage_scale =3D 1000, \ .entries =3D { \ @@ -120,7 +213,7 @@ static const unsigned long tegra210_cpu_max_freq_table[= ] =3D { { 0UL, { 0, 0, 0 } }, \ } =20 -#define CPU_CVB_TABLE_XA \ +#define T210_CPU_CVB_TABLE_XA \ .speedo_scale =3D 100, \ .voltage_scale =3D 1000, \ .entries =3D { \ @@ -143,7 +236,7 @@ static const unsigned long tegra210_cpu_max_freq_table[= ] =3D { { 0UL, { 0, 0, 0 } }, \ } =20 -#define CPU_CVB_TABLE_EUCM1 \ +#define T210_CPU_CVB_TABLE_EUCM1 \ .speedo_scale =3D 100, \ .voltage_scale =3D 1000, \ .entries =3D { \ @@ -166,7 +259,7 @@ static const unsigned long tegra210_cpu_max_freq_table[= ] =3D { { 0UL, { 0, 0, 0 } }, \ } =20 -#define CPU_CVB_TABLE_EUCM2 \ +#define T210_CPU_CVB_TABLE_EUCM2 \ .speedo_scale =3D 100, \ .voltage_scale =3D 1000, \ .entries =3D { \ @@ -188,7 +281,7 @@ static const unsigned long tegra210_cpu_max_freq_table[= ] =3D { { 0UL, { 0, 0, 0 } }, \ } =20 -#define CPU_CVB_TABLE_EUCM2_JOINT_RAIL \ +#define T210_CPU_CVB_TABLE_EUCM2_JOINT_RAIL \ .speedo_scale =3D 100, \ .voltage_scale =3D 1000, \ .entries =3D { \ @@ -209,7 +302,7 @@ static const unsigned long tegra210_cpu_max_freq_table[= ] =3D { { 0UL, { 0, 0, 0 } }, \ } =20 -#define CPU_CVB_TABLE_ODN \ +#define T210_CPU_CVB_TABLE_ODN \ .speedo_scale =3D 100, \ .voltage_scale =3D 1000, \ .entries =3D { \ @@ -238,7 +331,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { .process_id =3D 0, .min_millivolts =3D 840, .max_millivolts =3D 1120, - CPU_CVB_TABLE_EUCM2_JOINT_RAIL, + T210_CPU_CVB_TABLE_EUCM2_JOINT_RAIL, .cpu_dfll_data =3D { .tune0_low =3D 0xffead0ff, .tune0_high =3D 0xffead0ff, @@ -251,7 +344,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { .process_id =3D 1, .min_millivolts =3D 840, .max_millivolts =3D 1120, - CPU_CVB_TABLE_EUCM2_JOINT_RAIL, + T210_CPU_CVB_TABLE_EUCM2_JOINT_RAIL, .cpu_dfll_data =3D { .tune0_low =3D 0xffead0ff, .tune0_high =3D 0xffead0ff, @@ -264,7 +357,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { .process_id =3D 0, .min_millivolts =3D 900, .max_millivolts =3D 1162, - CPU_CVB_TABLE_EUCM2, + T210_CPU_CVB_TABLE_EUCM2, .cpu_dfll_data =3D { .tune0_low =3D 0xffead0ff, .tune0_high =3D 0xffead0ff, @@ -276,7 +369,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { .process_id =3D 1, .min_millivolts =3D 900, .max_millivolts =3D 1162, - CPU_CVB_TABLE_EUCM2, + T210_CPU_CVB_TABLE_EUCM2, .cpu_dfll_data =3D { .tune0_low =3D 0xffead0ff, .tune0_high =3D 0xffead0ff, @@ -288,7 +381,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { .process_id =3D 0, .min_millivolts =3D 900, .max_millivolts =3D 1195, - CPU_CVB_TABLE_EUCM2, + T210_CPU_CVB_TABLE_EUCM2, .cpu_dfll_data =3D { .tune0_low =3D 0xffead0ff, .tune0_high =3D 0xffead0ff, @@ -300,7 +393,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { .process_id =3D 1, .min_millivolts =3D 900, .max_millivolts =3D 1195, - CPU_CVB_TABLE_EUCM2, + T210_CPU_CVB_TABLE_EUCM2, .cpu_dfll_data =3D { .tune0_low =3D 0xffead0ff, .tune0_high =3D 0xffead0ff, @@ -312,7 +405,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { .process_id =3D 0, .min_millivolts =3D 841, .max_millivolts =3D 1227, - CPU_CVB_TABLE_EUCM1, + T210_CPU_CVB_TABLE_EUCM1, .cpu_dfll_data =3D { .tune0_low =3D 0xffead0ff, .tune0_high =3D 0xffead0ff, @@ -325,7 +418,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { .process_id =3D 1, .min_millivolts =3D 841, .max_millivolts =3D 1227, - CPU_CVB_TABLE_EUCM1, + T210_CPU_CVB_TABLE_EUCM1, .cpu_dfll_data =3D { .tune0_low =3D 0xffead0ff, .tune0_high =3D 0xffead0ff, @@ -338,7 +431,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { .process_id =3D 0, .min_millivolts =3D 870, .max_millivolts =3D 1150, - CPU_CVB_TABLE, + T210_CPU_CVB_TABLE, .cpu_dfll_data =3D { .tune0_low =3D 0xffead0ff, .tune1 =3D 0x20091d9, @@ -349,7 +442,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { .process_id =3D 1, .min_millivolts =3D 870, .max_millivolts =3D 1150, - CPU_CVB_TABLE, + T210_CPU_CVB_TABLE, .cpu_dfll_data =3D { .tune0_low =3D 0xffead0ff, .tune1 =3D 0x25501d0, @@ -360,7 +453,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { .process_id =3D 0, .min_millivolts =3D 818, .max_millivolts =3D 1227, - CPU_CVB_TABLE, + T210_CPU_CVB_TABLE, .cpu_dfll_data =3D { .tune0_low =3D 0xffead0ff, .tune0_high =3D 0xffead0ff, @@ -373,7 +466,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { .process_id =3D 1, .min_millivolts =3D 818, .max_millivolts =3D 1227, - CPU_CVB_TABLE, + T210_CPU_CVB_TABLE, .cpu_dfll_data =3D { .tune0_low =3D 0xffead0ff, .tune0_high =3D 0xffead0ff, @@ -386,7 +479,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { .process_id =3D -1, .min_millivolts =3D 918, .max_millivolts =3D 1113, - CPU_CVB_TABLE_XA, + T210_CPU_CVB_TABLE_XA, .cpu_dfll_data =3D { .tune0_low =3D 0xffead0ff, .tune1 =3D 0x17711BD, @@ -397,7 +490,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { .process_id =3D 0, .min_millivolts =3D 825, .max_millivolts =3D 1227, - CPU_CVB_TABLE_ODN, + T210_CPU_CVB_TABLE_ODN, .cpu_dfll_data =3D { .tune0_low =3D 0xffead0ff, .tune0_high =3D 0xffead0ff, @@ -410,7 +503,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { .process_id =3D 1, .min_millivolts =3D 825, .max_millivolts =3D 1227, - CPU_CVB_TABLE_ODN, + T210_CPU_CVB_TABLE_ODN, .cpu_dfll_data =3D { .tune0_low =3D 0xffead0ff, .tune0_high =3D 0xffead0ff, @@ -423,7 +516,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { .process_id =3D 0, .min_millivolts =3D 870, .max_millivolts =3D 1227, - CPU_CVB_TABLE, + T210_CPU_CVB_TABLE, .cpu_dfll_data =3D { .tune0_low =3D 0xffead0ff, .tune1 =3D 0x20091d9, @@ -434,7 +527,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { .process_id =3D 1, .min_millivolts =3D 870, .max_millivolts =3D 1227, - CPU_CVB_TABLE, + T210_CPU_CVB_TABLE, .cpu_dfll_data =3D { .tune0_low =3D 0xffead0ff, .tune1 =3D 0x25501d0, @@ -445,7 +538,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { .process_id =3D 0, .min_millivolts =3D 837, .max_millivolts =3D 1227, - CPU_CVB_TABLE, + T210_CPU_CVB_TABLE, .cpu_dfll_data =3D { .tune0_low =3D 0xffead0ff, .tune0_high =3D 0xffead0ff, @@ -458,7 +551,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { .process_id =3D 1, .min_millivolts =3D 837, .max_millivolts =3D 1227, - CPU_CVB_TABLE, + T210_CPU_CVB_TABLE, .cpu_dfll_data =3D { .tune0_low =3D 0xffead0ff, .tune0_high =3D 0xffead0ff, @@ -471,7 +564,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { .process_id =3D 0, .min_millivolts =3D 850, .max_millivolts =3D 1170, - CPU_CVB_TABLE, + T210_CPU_CVB_TABLE, .cpu_dfll_data =3D { .tune0_low =3D 0xffead0ff, .tune0_high =3D 0xffead0ff, @@ -484,7 +577,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { .process_id =3D 1, .min_millivolts =3D 850, .max_millivolts =3D 1170, - CPU_CVB_TABLE, + T210_CPU_CVB_TABLE, .cpu_dfll_data =3D { .tune0_low =3D 0xffead0ff, .tune0_high =3D 0xffead0ff, @@ -494,6 +587,13 @@ static struct cvb_table tegra210_cpu_cvb_tables[] =3D { }, }; =20 +static const struct dfll_fcpu_data tegra114_dfll_fcpu_data =3D { + .cpu_max_freq_table =3D tegra114_cpu_max_freq_table, + .cpu_max_freq_table_size =3D ARRAY_SIZE(tegra114_cpu_max_freq_table), + .cpu_cvb_tables =3D tegra114_cpu_cvb_tables, + .cpu_cvb_tables_size =3D ARRAY_SIZE(tegra114_cpu_cvb_tables) +}; + static const struct dfll_fcpu_data tegra124_dfll_fcpu_data =3D { .cpu_max_freq_table =3D tegra124_cpu_max_freq_table, .cpu_max_freq_table_size =3D ARRAY_SIZE(tegra124_cpu_max_freq_table), @@ -509,6 +609,10 @@ static const struct dfll_fcpu_data tegra210_dfll_fcpu_= data =3D { }; =20 static const struct of_device_id tegra124_dfll_fcpu_of_match[] =3D { + { + .compatible =3D "nvidia,tegra114-dfll", + .data =3D &tegra114_dfll_fcpu_data, + }, { .compatible =3D "nvidia,tegra124-dfll", .data =3D &tegra124_dfll_fcpu_data, --=20 2.48.1 From nobody Fri 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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afe492da4b9sm711067966b.63.2025.08.25.23.11.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Aug 2025 23:11:45 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd , "Rafael J. Wysocki" , Viresh Kumar , Philipp Zabel , Svyatoslav Ryhel Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 4/4] ARM: tegra: Add DFLL clock support for Tegra114 Date: Tue, 26 Aug 2025 09:11:17 +0300 Message-ID: <20250826061117.63643-5-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250826061117.63643-1-clamor95@gmail.com> References: <20250826061117.63643-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add DFLL clock node to common Tegra114 device tree along with clocks property to cpu node. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- arch/arm/boot/dts/nvidia/tegra114.dtsi | 33 ++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvi= dia/tegra114.dtsi index 4caf2073c556..c429478eb122 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include #include =20 / { @@ -693,6 +694,29 @@ mipi: mipi@700e3000 { #nvidia,mipi-calibrate-cells =3D <1>; }; =20 + dfll: clock@70110000 { + compatible =3D "nvidia,tegra114-dfll"; + reg =3D <0x70110000 0x100>, /* DFLL control */ + <0x70110000 0x100>, /* I2C output control */ + <0x70110100 0x100>, /* Integrated I2C controller */ + <0x70110200 0x100>; /* Look-up table RAM */ + interrupts =3D ; + clocks =3D <&tegra_car TEGRA114_CLK_DFLL_SOC>, + <&tegra_car TEGRA114_CLK_DFLL_REF>, + <&tegra_car TEGRA114_CLK_I2C5>; + clock-names =3D "soc", "ref", "i2c"; + resets =3D <&tegra_car TEGRA114_RST_DFLL_DVCO>; + reset-names =3D "dvco"; + #clock-cells =3D <0>; + clock-output-names =3D "dfllCPU_out"; + nvidia,droop-ctrl =3D <0x00000f00>; + nvidia,force-mode =3D <1>; + nvidia,cf =3D <10>; + nvidia,ci =3D <0>; + nvidia,cg =3D <2>; + status =3D "disabled"; + }; + mmc@78000000 { compatible =3D "nvidia,tegra114-sdhci"; reg =3D <0x78000000 0x200>; @@ -824,6 +848,15 @@ cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a15"; reg =3D <0>; + + clocks =3D <&tegra_car TEGRA114_CLK_CCLK_G>, + <&tegra_car TEGRA114_CLK_CCLK_LP>, + <&tegra_car TEGRA114_CLK_PLL_X>, + <&tegra_car TEGRA114_CLK_PLL_P>, + <&dfll>; + clock-names =3D "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; + /* FIXME: what's the actual transition time? */ + clock-latency =3D <300000>; }; =20 cpu1: cpu@1 { --=20 2.48.1