Most publicly available Amlogic datasheets mention that the CPU employs
a architecture, quad-core ARM Cortex-A53 and ARM Cortex A55 and
Cortex-A73 and Cortex-A53 cluster, sharing a unified L2 cache to enhance
overall system performance.

However, these documents typically omit details regarding the sizes of the
L1 data cache, L1 instruction cache, and L2 cache.

The patches in question align with the cache specifications provided by
ARM TRM for the respective CPU cores.

ARM Cortex-A53
L1: 32KB instruction + 32KB data cache
L2: Unified 512KB cache
L1 cache details, L2 cache details

[1] https://developer.arm.com/documentation/ddi0500/j/Level-1-Memory-System/About-the-L1-memory-system?lang=en
[2] https://developer.arm.com/documentation/ddi0500/j/Level-2-Memory-System/About-the-L2-memory-system?lang=en

ARM Cortex-A55
Cache sizes are implementation-dependent; refer to ARM documentation for configuration options.

[3] https://developer.arm.com/documentation/100442/0200/Functional-description/Introduction-to-the-Cortex-A55-core/Implementation-options

ARM Cortex-A73 (as used in Amlogic S922X and T7)
L1: Configurable, typically 64KB instruction + 64KB data
L2: Unified cache, configurable up to 1MB or more
L2 cache details,
4× Cortex-A73 cores (up to 1.8GHz) with 1MB shared L2 cache
2× Cortex-A53 cores with 256KB shared L2 cache

[4] https://developer.arm.com/documentation/100048/0100/level-1-memory-system/about-the-l1-memory-system?lang=enL2
[5] https://developer.arm.com/documentation/100048/0100/level-2-memory-system/about-the-l2-memory-system?lang=en
[6] https://androidpctv.com/comparative-amlogic-s922x/

Changes:
v2: Modified the commit message and added cache information few more SoC.

v1: https://lists.infradead.org/pipermail/linux-arm-kernel/2024-February/901497.html

Thanks
-Anand

Anand Moon (11):
  arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL
    SoC
  arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC
  arm64: dts: amlogic: Add cache information to the Amlogic G12A SoCS
  arm64: dts: amlogic: Add cache information to the Amlogic AXG SoCS
  arm64: dts: amlogic: Add cache information to the Amlogic GXM SoCS
  arm64: dts: amlogic: Add cache information to the Amlogic A1 SoC
  arm64: dts: amlogic: Add cache information to the Amlogic A4 SoC
  arm64: dts: amlogic: Add cache information to the Amlogic C3 SoC
  arm64: dts: amlogic: Add cache information to the Amlogic S7 SoC
  arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC
  arm64: dts: amlogic: Add cache information to the Amlogic T7 SoC

 arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 37 +++++++++++
 arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 23 +++++++
 arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 36 ++++++++++
 arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 74 +++++++++++++++++++++
 arch/arm64/boot/dts/amlogic/meson-a1.dtsi   | 15 +++++
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi  | 21 ++++++
 arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 27 ++++++++
 arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 62 +++++++++++++++--
 arch/arm64/boot/dts/amlogic/meson-gx.dtsi   | 27 ++++++++
 arch/arm64/boot/dts/amlogic/meson-gxm.dtsi  | 24 +++++++
 arch/arm64/boot/dts/amlogic/meson-sm1.dtsi  | 27 ++++++++
 11 files changed, 366 insertions(+), 7 deletions(-)


base-commit: 1b237f190eb3d36f52dffe07a40b5eb210280e00
-- 
2.50.1

Hi,

On Mon, 25 Aug 2025 12:21:40 +0530, Anand Moon wrote:
> Most publicly available Amlogic datasheets mention that the CPU employs
> a architecture, quad-core ARM Cortex-A53 and ARM Cortex A55 and
> Cortex-A73 and Cortex-A53 cluster, sharing a unified L2 cache to enhance
> overall system performance.
> 
> However, these documents typically omit details regarding the sizes of the
> L1 data cache, L1 instruction cache, and L2 cache.
> 
> [...]

Thanks, Applied to https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git (v6.18/arm64-dt)

[01/11] arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL SoC
        https://git.kernel.org/amlogic/c/d7fc05da8ba28d22fb9bd79d9308f928fcb81c19
[02/11] arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC
        https://git.kernel.org/amlogic/c/fd7b48b1f91e1830e22e73744e7525af24d8ae25
[03/11] arm64: dts: amlogic: Add cache information to the Amlogic G12A SoCS
        https://git.kernel.org/amlogic/c/a4428e52babdb682f47f99b0b816e227e51a3835
[04/11] arm64: dts: amlogic: Add cache information to the Amlogic AXG SoCS
        https://git.kernel.org/amlogic/c/3b6ad2a433672f4ed9e1c90e4ae6b94683d1f1a2
[05/11] arm64: dts: amlogic: Add cache information to the Amlogic GXM SoCS
        https://git.kernel.org/amlogic/c/fe2c12bc0a8f9e5db87bfbf231658eadef4cdd47
[06/11] arm64: dts: amlogic: Add cache information to the Amlogic A1 SoC
        https://git.kernel.org/amlogic/c/2d97773212f8516b2fe3177077b1ecf7b67a4e09
[07/11] arm64: dts: amlogic: Add cache information to the Amlogic A4 SoC
        https://git.kernel.org/amlogic/c/57273dc063d5a80e8cebc20878369099992be01a
[08/11] arm64: dts: amlogic: Add cache information to the Amlogic C3 SoC
        https://git.kernel.org/amlogic/c/6d4ab38a0a21c82076105e4cc37087ef92253c7b
[09/11] arm64: dts: amlogic: Add cache information to the Amlogic S7 SoC
        https://git.kernel.org/amlogic/c/494c362fa1633bba127045ace8f0eea0b277af28
[10/11] arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC
        https://git.kernel.org/amlogic/c/e7f85e6c155aed3e10e698dd05bd04b2d52edb59
[11/11] arm64: dts: amlogic: Add cache information to the Amlogic T7 SoC
        https://git.kernel.org/amlogic/c/e97fdb9b8a0f8bd349de48815694f8a7200e3d62

These changes has been applied on the intermediate git tree [1].

The v6.18/arm64-dt branch will then be sent via a formal Pull Request to the Linux SoC maintainers
for inclusion in their intermediate git branches in order to be sent to Linus during
the next merge window, or sooner if it's a set of fixes.

In the cases of fixes, those will be merged in the current release candidate
kernel and as soon they appear on the Linux master branch they will be
backported to the previous Stable and Long-Stable kernels [2].

The intermediate git branches are merged daily in the linux-next tree [3],
people are encouraged testing these pre-release kernels and report issues on the
relevant mailing-lists.

If problems are discovered on those changes, please submit a signed-off-by revert
patch followed by a corrective changeset.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
[3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git

-- 
Neil

Hi Neil,

On Thu, 4 Sept 2025 at 18:58, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>
> Hi,
>
> On Mon, 25 Aug 2025 12:21:40 +0530, Anand Moon wrote:
> > Most publicly available Amlogic datasheets mention that the CPU employs
> > a architecture, quad-core ARM Cortex-A53 and ARM Cortex A55 and
> > Cortex-A73 and Cortex-A53 cluster, sharing a unified L2 cache to enhance
> > overall system performance.
> >
> > However, these documents typically omit details regarding the sizes of the
> > L1 data cache, L1 instruction cache, and L2 cache.
> >
> > [...]
>
> Thanks, Applied to https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git (v6.18/arm64-dt)
>
> [01/11] arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL SoC
>         https://git.kernel.org/amlogic/c/d7fc05da8ba28d22fb9bd79d9308f928fcb81c19
> [02/11] arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC
>         https://git.kernel.org/amlogic/c/fd7b48b1f91e1830e22e73744e7525af24d8ae25
> [03/11] arm64: dts: amlogic: Add cache information to the Amlogic G12A SoCS
>         https://git.kernel.org/amlogic/c/a4428e52babdb682f47f99b0b816e227e51a3835
> [04/11] arm64: dts: amlogic: Add cache information to the Amlogic AXG SoCS
>         https://git.kernel.org/amlogic/c/3b6ad2a433672f4ed9e1c90e4ae6b94683d1f1a2
> [05/11] arm64: dts: amlogic: Add cache information to the Amlogic GXM SoCS
>         https://git.kernel.org/amlogic/c/fe2c12bc0a8f9e5db87bfbf231658eadef4cdd47
> [06/11] arm64: dts: amlogic: Add cache information to the Amlogic A1 SoC
>         https://git.kernel.org/amlogic/c/2d97773212f8516b2fe3177077b1ecf7b67a4e09
> [07/11] arm64: dts: amlogic: Add cache information to the Amlogic A4 SoC
>         https://git.kernel.org/amlogic/c/57273dc063d5a80e8cebc20878369099992be01a
> [08/11] arm64: dts: amlogic: Add cache information to the Amlogic C3 SoC
>         https://git.kernel.org/amlogic/c/6d4ab38a0a21c82076105e4cc37087ef92253c7b
> [09/11] arm64: dts: amlogic: Add cache information to the Amlogic S7 SoC
>         https://git.kernel.org/amlogic/c/494c362fa1633bba127045ace8f0eea0b277af28
> [10/11] arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC
>         https://git.kernel.org/amlogic/c/e7f85e6c155aed3e10e698dd05bd04b2d52edb59
> [11/11] arm64: dts: amlogic: Add cache information to the Amlogic T7 SoC
>         https://git.kernel.org/amlogic/c/e97fdb9b8a0f8bd349de48815694f8a7200e3d62
>
> These changes has been applied on the intermediate git tree [1].
>
> The v6.18/arm64-dt branch will then be sent via a formal Pull Request to the Linux SoC maintainers
> for inclusion in their intermediate git branches in order to be sent to Linus during
> the next merge window, or sooner if it's a set of fixes.
>
> In the cases of fixes, those will be merged in the current release candidate
> kernel and as soon they appear on the Linux master branch they will be
> backported to the previous Stable and Long-Stable kernels [2].
>
> The intermediate git branches are merged daily in the linux-next tree [3],
> people are encouraged testing these pre-release kernels and report issues on the
> relevant mailing-lists.
>
> If problems are discovered on those changes, please submit a signed-off-by revert
> patch followed by a corrective changeset.
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git
> [2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
> [3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
>
Received feedback from Krzysztof to omit the comments in the commit message.
Should I respin accordingly?
> --
> Neil
>
Thanks
-Anand

On 05/09/2025 06:01, Anand Moon wrote:
> Hi Neil,
> 
> On Thu, 4 Sept 2025 at 18:58, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>>
>> Hi,
>>
>> On Mon, 25 Aug 2025 12:21:40 +0530, Anand Moon wrote:
>>> Most publicly available Amlogic datasheets mention that the CPU employs
>>> a architecture, quad-core ARM Cortex-A53 and ARM Cortex A55 and
>>> Cortex-A73 and Cortex-A53 cluster, sharing a unified L2 cache to enhance
>>> overall system performance.
>>>
>>> However, these documents typically omit details regarding the sizes of the
>>> L1 data cache, L1 instruction cache, and L2 cache.
>>>
>>> [...]
>>
>> Thanks, Applied to https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git (v6.18/arm64-dt)
>>
>> [01/11] arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL SoC
>>          https://git.kernel.org/amlogic/c/d7fc05da8ba28d22fb9bd79d9308f928fcb81c19
>> [02/11] arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC
>>          https://git.kernel.org/amlogic/c/fd7b48b1f91e1830e22e73744e7525af24d8ae25
>> [03/11] arm64: dts: amlogic: Add cache information to the Amlogic G12A SoCS
>>          https://git.kernel.org/amlogic/c/a4428e52babdb682f47f99b0b816e227e51a3835
>> [04/11] arm64: dts: amlogic: Add cache information to the Amlogic AXG SoCS
>>          https://git.kernel.org/amlogic/c/3b6ad2a433672f4ed9e1c90e4ae6b94683d1f1a2
>> [05/11] arm64: dts: amlogic: Add cache information to the Amlogic GXM SoCS
>>          https://git.kernel.org/amlogic/c/fe2c12bc0a8f9e5db87bfbf231658eadef4cdd47
>> [06/11] arm64: dts: amlogic: Add cache information to the Amlogic A1 SoC
>>          https://git.kernel.org/amlogic/c/2d97773212f8516b2fe3177077b1ecf7b67a4e09
>> [07/11] arm64: dts: amlogic: Add cache information to the Amlogic A4 SoC
>>          https://git.kernel.org/amlogic/c/57273dc063d5a80e8cebc20878369099992be01a
>> [08/11] arm64: dts: amlogic: Add cache information to the Amlogic C3 SoC
>>          https://git.kernel.org/amlogic/c/6d4ab38a0a21c82076105e4cc37087ef92253c7b
>> [09/11] arm64: dts: amlogic: Add cache information to the Amlogic S7 SoC
>>          https://git.kernel.org/amlogic/c/494c362fa1633bba127045ace8f0eea0b277af28
>> [10/11] arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC
>>          https://git.kernel.org/amlogic/c/e7f85e6c155aed3e10e698dd05bd04b2d52edb59
>> [11/11] arm64: dts: amlogic: Add cache information to the Amlogic T7 SoC
>>          https://git.kernel.org/amlogic/c/e97fdb9b8a0f8bd349de48815694f8a7200e3d62
>>
>> These changes has been applied on the intermediate git tree [1].
>>
>> The v6.18/arm64-dt branch will then be sent via a formal Pull Request to the Linux SoC maintainers
>> for inclusion in their intermediate git branches in order to be sent to Linus during
>> the next merge window, or sooner if it's a set of fixes.
>>
>> In the cases of fixes, those will be merged in the current release candidate
>> kernel and as soon they appear on the Linux master branch they will be
>> backported to the previous Stable and Long-Stable kernels [2].
>>
>> The intermediate git branches are merged daily in the linux-next tree [3],
>> people are encouraged testing these pre-release kernels and report issues on the
>> relevant mailing-lists.
>>
>> If problems are discovered on those changes, please submit a signed-off-by revert
>> patch followed by a corrective changeset.
>>
>> [1] https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git
>> [2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
>> [3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
>>
> Received feedback from Krzysztof to omit the comments in the commit message.
> Should I respin accordingly?

Sure, I'll re-apply the new version

Neil

>> --
>> Neil
>>
> Thanks
> -Anand