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Sun, 24 Aug 2025 23:52:55 -0700 (PDT) From: Anand Moon To: Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Amlogic Meson SoC support), linux-amlogic@lists.infradead.org (open list:ARM/Amlogic Meson SoC support), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [PATCH v2 01/11] arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL SoC Date: Mon, 25 Aug 2025 12:21:41 +0530 Message-ID: <20250825065240.22577-2-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250825065240.22577-1-linux.amoon@gmail.com> References: <20250825065240.22577-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As per S905 and S905X datasheet add missing cache information to the Amlogic GXBB and GXL SoC. - Each Cortex-A53 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 512KB Unified L2 cache. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon --- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 27 +++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dt= s/amlogic/meson-gx.dtsi index 7d99ca44e660..c1d8e81d95cb 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -95,6 +95,12 @@ cpu0: cpu@0 { compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x0>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; next-level-cache =3D <&l2>; clocks =3D <&scpi_dvfs 0>; #cooling-cells =3D <2>; @@ -105,6 +111,12 @@ cpu1: cpu@1 { compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x1>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; next-level-cache =3D <&l2>; clocks =3D <&scpi_dvfs 0>; #cooling-cells =3D <2>; @@ -115,6 +127,12 @@ cpu2: cpu@2 { compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x2>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; next-level-cache =3D <&l2>; clocks =3D <&scpi_dvfs 0>; #cooling-cells =3D <2>; @@ -125,6 +143,12 @@ cpu3: cpu@3 { compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x3>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; next-level-cache =3D <&l2>; clocks =3D <&scpi_dvfs 0>; #cooling-cells =3D <2>; @@ -134,6 +158,9 @@ l2: l2-cache0 { compatible =3D "cache"; cache-level =3D <2>; cache-unified; + cache-size =3D <0x80000>; /* L2. 512 KB */ + cache-line-size =3D <64>; + cache-sets =3D <512>; }; }; =20 --=20 2.50.1 From nobody Fri Oct 3 20:48:05 2025 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C511F2868B3; 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Sun, 24 Aug 2025 23:53:04 -0700 (PDT) Received: from rockpi-5b ([45.112.0.216]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-770401ecc51sm6604072b3a.75.2025.08.24.23.52.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Aug 2025 23:53:03 -0700 (PDT) From: Anand Moon To: Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Amlogic Meson SoC support), linux-amlogic@lists.infradead.org (open list:ARM/Amlogic Meson SoC support), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [PATCH v2 02/11] arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC Date: Mon, 25 Aug 2025 12:21:42 +0530 Message-ID: <20250825065240.22577-3-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250825065240.22577-1-linux.amoon@gmail.com> References: <20250825065240.22577-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As per S905X3 datasheet add missing cache information to the Amlogic SM1 SoC. ARM Cortex-A55 CPU uses unified L3 cache instead of L2 cache. - Each Cortex-A55 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 256KB Unified L2 cache. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon --- arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/d= ts/amlogic/meson-sm1.dtsi index 966ebb19cc55..e5db8ce94062 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -55,6 +55,12 @@ cpu0: cpu@0 { compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x0>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; next-level-cache =3D <&l2>; #cooling-cells =3D <2>; }; @@ -64,6 +70,12 @@ cpu1: cpu@1 { compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x1>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; next-level-cache =3D <&l2>; #cooling-cells =3D <2>; }; @@ -73,6 +85,12 @@ cpu2: cpu@2 { compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x2>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; next-level-cache =3D <&l2>; #cooling-cells =3D <2>; }; @@ -82,6 +100,12 @@ cpu3: cpu@3 { compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x3>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; next-level-cache =3D <&l2>; #cooling-cells =3D <2>; }; @@ -90,6 +114,9 @@ l2: l2-cache0 { compatible =3D "cache"; cache-level =3D <2>; cache-unified; + cache-size =3D <0x40000>; /* L2. 256 KB */ + cache-line-size =3D <64>; + cache-sets =3D <256>; }; }; =20 --=20 2.50.1 From nobody Fri Oct 3 20:48:05 2025 Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A56AC2882DE; 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charset="utf-8" As per the S905X2 datasheet add missing cache information to the Amlogic G12A SoC. - Each Cortex-A53 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 512KB Unified L2 cache. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon --- arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 27 +++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/= dts/amlogic/meson-g12a.dtsi index deee61dbe074..1321ad95923d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -17,6 +17,12 @@ cpu0: cpu@0 { compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x0>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; next-level-cache =3D <&l2>; #cooling-cells =3D <2>; }; @@ -26,6 +32,12 @@ cpu1: cpu@1 { compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x1>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; next-level-cache =3D <&l2>; #cooling-cells =3D <2>; }; @@ -35,6 +47,12 @@ cpu2: cpu@2 { compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x2>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; next-level-cache =3D <&l2>; #cooling-cells =3D <2>; }; @@ -44,6 +62,12 @@ cpu3: cpu@3 { compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x3>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; next-level-cache =3D <&l2>; #cooling-cells =3D <2>; }; @@ -52,6 +76,9 @@ l2: l2-cache0 { compatible =3D "cache"; cache-level =3D <2>; cache-unified; + cache-size =3D <0x80000>; /* L2. 512 KB */ + cache-line-size =3D <64>; + cache-sets =3D <512>; }; }; =20 --=20 2.50.1 From nobody Fri Oct 3 20:48:05 2025 Received: from mail-pf1-f171.google.com (mail-pf1-f171.google.com [209.85.210.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F841286436; 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charset="utf-8" As per the AXG datasheet add missing cache information to the Amlogic AXG SoC. - Each Cortex-A53 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 512KB Unified L2 cache. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/d= ts/amlogic/meson-axg.dtsi index 2df143aa77ce..04fb130ac7c6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -83,6 +83,12 @@ cpu1: cpu@1 { compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x1>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; next-level-cache =3D <&l2>; clocks =3D <&scpi_dvfs 0>; dynamic-power-coefficient =3D <140>; @@ -94,6 +100,12 @@ cpu2: cpu@2 { compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x2>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; 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charset="utf-8" As per the GXM datasheet add missing cache information to the Amlogic GXM SoC. - Each Cortex-A53 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 512KB Unified L2 cache. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon --- arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/d= ts/amlogic/meson-gxm.dtsi index 411cc312fc62..514c9bea6423 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi @@ -64,6 +64,12 @@ cpu4: cpu@100 { reg =3D <0x0 0x100>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; next-level-cache =3D <&l2>; clocks =3D <&scpi_dvfs 1>; #cooling-cells =3D <2>; @@ -75,6 +81,12 @@ cpu5: cpu@101 { reg =3D <0x0 0x101>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; 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charset="utf-8" As per the A1 datasheet add missing cache information to the Amlogic A1 SoC. - Each Cortex-A53 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 512KB Unified L2 cache. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dt= s/amlogic/meson-a1.dtsi index f7f25a10f409..27b68ed85c4c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -27,6 +27,12 @@ cpu0: cpu@0 { compatible =3D "arm,cortex-a35"; reg =3D <0x0 0x0>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; next-level-cache =3D <&l2>; #cooling-cells =3D <2>; }; @@ -36,6 +42,12 @@ cpu1: cpu@1 { compatible =3D "arm,cortex-a35"; reg =3D <0x0 0x1>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; next-level-cache =3D <&l2>; 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charset="utf-8" As per A4 datasheet add missing cache information to the Amlogic A4 SoC. - Each Cortex-A53 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 512KB Unified L2 cache. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon --- arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 37 +++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-a4.dtsi index 563bc2e662fa..fce45933fa28 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi @@ -17,6 +17,13 @@ cpu0: cpu@0 { compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x0>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2>; }; =20 cpu1: cpu@1 { @@ -24,6 +31,13 @@ cpu1: cpu@1 { compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x1>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2>; 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Sun, 24 Aug 2025 23:53:49 -0700 (PDT) Received: from rockpi-5b ([45.112.0.216]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-770401ecc51sm6604072b3a.75.2025.08.24.23.53.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Aug 2025 23:53:48 -0700 (PDT) From: Anand Moon To: Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Amlogic Meson SoC support), linux-amlogic@lists.infradead.org (open list:ARM/Amlogic Meson SoC support), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [PATCH v2 08/11] arm64: dts: amlogic: Add cache information to the Amlogic C3 SoC Date: Mon, 25 Aug 2025 12:21:48 +0530 Message-ID: <20250825065240.22577-9-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250825065240.22577-1-linux.amoon@gmail.com> References: <20250825065240.22577-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As per C3 datasheet add missing cache information to the Amlogic C3 SoC. - Each Cortex-A53 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 512KB Unified L2 cache. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon --- arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 23 +++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-c3.dtsi index cb9ea3ca6ee0..ee0b1ffa947e 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi @@ -23,6 +23,13 @@ cpu0: cpu@0 { compatible =3D "arm,cortex-a35"; reg =3D <0x0 0x0>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2>; }; =20 cpu1: cpu@1 { @@ -30,6 +37,22 @@ cpu1: cpu@1 { compatible =3D "arm,cortex-a35"; reg =3D <0x0 0x1>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2>; 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Sun, 24 Aug 2025 23:53:55 -0700 (PDT) From: Anand Moon To: Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Amlogic Meson SoC support), linux-amlogic@lists.infradead.org (open list:ARM/Amlogic Meson SoC support), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [PATCH v2 09/11] arm64: dts: amlogic: Add cache information to the Amlogic S7 SoC Date: Mon, 25 Aug 2025 12:21:49 +0530 Message-ID: <20250825065240.22577-10-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250825065240.22577-1-linux.amoon@gmail.com> References: <20250825065240.22577-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As per S7 datasheet add missing cache information to the Amlogic S7 SoC. ARM Cortex-A55 CPU uses unified L2 cache. - Each Cortex-A55 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 256KB Unified L2 cache. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon --- arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 36 +++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-s7.dtsi index 260918b37b9a..d262c0b66e4b 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi @@ -18,6 +18,13 @@ cpu0: cpu@0 { compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x0>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2>; }; =20 cpu1: cpu@100 { @@ -25,6 +32,13 @@ cpu1: cpu@100 { compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x100>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2>; }; =20 cpu2: cpu@200 { @@ -32,6 +46,13 @@ cpu2: cpu@200 { compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x200>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2>; }; =20 cpu3: cpu@300 { @@ -39,8 +60,23 @@ cpu3: cpu@300 { compatible =3D "arm,cortex-a55"; reg =3D <0x0 0x300>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2>; }; =20 + l2: l2-cache0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x40000>; /* L2. 256 KB */ + cache-line-size =3D <64>; + cache-sets =3D <512>; + }; }; =20 timer { --=20 2.50.1 From nobody Fri Oct 3 20:48:05 2025 Received: from mail-pf1-f170.google.com (mail-pf1-f170.google.com [209.85.210.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEC4528850C; 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charset="utf-8" As per S922X datasheet add missing cache information to the Amlogic S922X SoC. - Each Cortex-A53 core has 32 KB of instruction cache and 32 KB of L1 data cache available. - Each Cortex-A73 core has 64 KB of L1 instruction cache and 64 KB of L1 data cache available. - The little (A53) cluster has 256 KB of unified L2 cache available. - The big (A73) cluster has 1 MB of unified L2 cache available. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon --- arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 62 ++++++++++++++++++--- 1 file changed, 55 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/= dts/amlogic/meson-g12b.dtsi index 86e6ceb31d5e..f04efa828256 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi @@ -49,7 +49,13 @@ cpu0: cpu@0 { reg =3D <0x0 0x0>; enable-method =3D "psci"; capacity-dmips-mhz =3D <592>; - next-level-cache =3D <&l2>; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2_cache_l>; #cooling-cells =3D <2>; }; =20 @@ -59,7 +65,13 @@ cpu1: cpu@1 { reg =3D <0x0 0x1>; enable-method =3D "psci"; capacity-dmips-mhz =3D <592>; - next-level-cache =3D <&l2>; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2_cache_l>; #cooling-cells =3D <2>; }; =20 @@ -69,7 +81,13 @@ cpu100: cpu@100 { reg =3D <0x0 0x100>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&l2>; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2_cache_l>; #cooling-cells =3D <2>; }; =20 @@ -79,7 +97,13 @@ cpu101: cpu@101 { reg =3D <0x0 0x101>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&l2>; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2_cache_l>; #cooling-cells =3D <2>; }; =20 @@ -89,7 +113,13 @@ cpu102: cpu@102 { reg =3D <0x0 0x102>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&l2>; + d-cache-line-size =3D <64>; + d-cache-size =3D <0x10000>; + d-cache-sets =3D <64>; + i-cache-line-size =3D <64>; + i-cache-size =3D <0x10000>; + i-cache-sets =3D <64>; + next-level-cache =3D <&l2_cache_b>; #cooling-cells =3D <2>; }; =20 @@ -99,14 +129,32 @@ cpu103: cpu@103 { reg =3D <0x0 0x103>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&l2>; + d-cache-line-size =3D <64>; + d-cache-size =3D <0x10000>; + d-cache-sets =3D <64>; + i-cache-line-size =3D <64>; + i-cache-size =3D <0x10000>; + i-cache-sets =3D <64>; + next-level-cache =3D <&l2_cache_b>; #cooling-cells =3D <2>; }; =20 - l2: l2-cache0 { + l2_cache_l: l2-cache-cluster0 { compatible =3D "cache"; cache-level =3D <2>; cache-unified; + cache-size =3D <0x40000>; /* L2. 256 KB */ + cache-line-size =3D <64>; + cache-sets =3D <512>; + }; + + l2_cache_b: l2-cache-cluster1 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x100000>; 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Sun, 24 Aug 2025 23:54:11 -0700 (PDT) From: Anand Moon To: Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Amlogic Meson SoC support), linux-amlogic@lists.infradead.org (open list:ARM/Amlogic Meson SoC support), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [PATCH v2 11/11] arm64: dts: amlogic: Add cache information to the Amlogic T7 SoC Date: Mon, 25 Aug 2025 12:21:51 +0530 Message-ID: <20250825065240.22577-12-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250825065240.22577-1-linux.amoon@gmail.com> References: <20250825065240.22577-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As per T7 datasheet add missing cache information to the Amlogic T7 SoC. - Each Cortex-A53 core has 32 KB of instruction cache and 32 KB of L1 data cache available. - Each Cortex-A73 core has 64 KB of L1 instruction cache and 64 KB of L1 data cache available. - The little (A53) cluster has 256 KB of unified L2 cache available. - The big (A73) cluster has 1 MB of unified L2 cache available. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon --- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 74 +++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-t7.dtsi index ec743cad57db..6510068bcff9 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -53,6 +53,13 @@ cpu100: cpu@100 { compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x100>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2_cache_l>; }; =20 cpu101: cpu@101 { @@ -60,6 +67,13 @@ cpu101: cpu@101 { compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x101>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2_cache_l>; }; =20 cpu102: cpu@102 { @@ -67,6 +81,13 @@ cpu102: cpu@102 { compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x102>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2_cache_l>; }; =20 cpu103: cpu@103 { @@ -74,6 +95,13 @@ cpu103: cpu@103 { compatible =3D "arm,cortex-a53"; reg =3D <0x0 0x103>; enable-method =3D "psci"; + d-cache-line-size =3D <32>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <32>; + i-cache-line-size =3D <32>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <32>; + next-level-cache =3D <&l2_cache_l>; }; =20 cpu0: cpu@0 { @@ -81,6 +109,13 @@ cpu0: cpu@0 { compatible =3D "arm,cortex-a73"; reg =3D <0x0 0x0>; enable-method =3D "psci"; + d-cache-line-size =3D <64>; + d-cache-size =3D <0x10000>; + d-cache-sets =3D <64>; + i-cache-line-size =3D <64>; + i-cache-size =3D <0x10000>; + i-cache-sets =3D <64>; + next-level-cache =3D <&l2_cache_b>; }; =20 cpu1: cpu@1 { @@ -88,6 +123,13 @@ cpu1: cpu@1 { compatible =3D "arm,cortex-a73"; reg =3D <0x0 0x1>; enable-method =3D "psci"; + d-cache-line-size =3D <64>; + d-cache-size =3D <0x10000>; + d-cache-sets =3D <64>; + i-cache-line-size =3D <64>; + i-cache-size =3D <0x10000>; + i-cache-sets =3D <64>; + next-level-cache =3D <&l2_cache_b>; }; =20 cpu2: cpu@2 { @@ -95,6 +137,13 @@ cpu2: cpu@2 { compatible =3D "arm,cortex-a73"; reg =3D <0x0 0x2>; enable-method =3D "psci"; + d-cache-line-size =3D <64>; + d-cache-size =3D <0x10000>; + d-cache-sets =3D <64>; + i-cache-line-size =3D <64>; + i-cache-size =3D <0x10000>; + i-cache-sets =3D <64>; + next-level-cache =3D <&l2_cache_b>; }; =20 cpu3: cpu@3 { @@ -102,6 +151,31 @@ cpu3: cpu@3 { compatible =3D "arm,cortex-a73"; reg =3D <0x0 0x3>; enable-method =3D "psci"; + d-cache-line-size =3D <64>; + d-cache-size =3D <0x10000>; + d-cache-sets =3D <64>; + i-cache-line-size =3D <64>; + i-cache-size =3D <0x10000>; + i-cache-sets =3D <64>; + next-level-cache =3D <&l2_cache_b>; + }; + + l2_cache_l: l2-cache-cluster0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x40000>; /* L2. 256 KB */ + cache-line-size =3D <64>; + cache-sets =3D <512>; + }; + + l2_cache_b: l2-cache-cluster1 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x100000>; /* L2. 1 Mb */ + cache-line-size =3D <64>; + cache-sets =3D <512>; }; }; =20 --=20 2.50.1