On Wed, Aug 20, 2025 at 08:39:36AM +0300, Svyatoslav Ryhel wrote:
> вт, 19 серп. 2025 р. о 23:30 Rob Herring <robh@kernel.org> пише:
> >
> > On Tue, Aug 19, 2025 at 03:16:29PM +0300, Svyatoslav Ryhel wrote:
> > > Document CSI hw block found in Tegra20 and Tegra30 SoC.
> > >
> > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> > > ---
> > > .../display/tegra/nvidia,tegra210-csi.yaml | 78 +++++++++++++++----
> > > 1 file changed, 63 insertions(+), 15 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml
> > > index fa07a40d1004..a5669447a33b 100644
> > > --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml
> > > +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml
> > > @@ -16,30 +16,78 @@ properties:
> > >
> > > compatible:
> > > enum:
> > > + - nvidia,tegra20-csi
> > > + - nvidia,tegra30-csi
> > > - nvidia,tegra210-csi
> > >
> > > reg:
> > > maxItems: 1
> > >
> > > - clocks:
> > > - items:
> > > - - description: module clock
> > > - - description: A/B lanes clock
> > > - - description: C/D lanes clock
> > > - - description: E lane clock
> > > - - description: test pattern generator clock
> > > -
> > > - clock-names:
> > > - items:
> > > - - const: csi
> > > - - const: cilab
> > > - - const: cilcd
> > > - - const: cile
> > > - - const: csi_tpg
> > > + clocks: true
> > > + clock-names: true
> > >
> > > power-domains:
> > > maxItems: 1
> > >
> > > +allOf:
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + enum:
> > > + - nvidia,tegra20-csi
> > > + then:
> > > + properties:
> > > + clocks:
> > > + items:
> > > + - description: module clock
> > > +
> > > + clock-names:
> > > + items:
> > > + - const: csi
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + enum:
> > > + - nvidia,tegra30-csi
> > > + then:
> > > + properties:
> > > + clocks:
> > > + items:
> > > + - description: module clock
> > > + - description: PAD A clock
> > > + - description: PAD B clock
> > > +
> > > + clock-names:
> > > + items:
> > > + - const: csi
> > > + - const: csia_pad
> > > + - const: csib_pad
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + enum:
> > > + - nvidia,tegra210-csi
> > > + then:
> > > + properties:
> > > + clocks:
> > > + items:
> > > + - description: module clock
> > > + - description: A/B lanes clock
> > > + - description: C/D lanes clock
> > > + - description: E lane clock
> > > + - description: test pattern generator clock
> > > +
> > > + clock-names:
> > > + items:
> > > + - const: csi
> > > + - const: cilab
> > > + - const: cilcd
> > > + - const: cile
> > > + - const: csi_tpg
> > > +
> >
> > This is longer that what's the same. I think this should be a separate
> > schema doc.
> >
>
> CSI hw block configuration is similar between generations, the main
> difference is the amount of clocks routed. Not sure if it is worth it
> to create duplicates with sole difference in number of clocks used.
If the clock names were at least the same I might agree, but the only
common one is 'csi'. How similar the h/w is doesn't matter, how similar
the binding is is what matters.
Rob