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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.17.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:17:11 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 17/19] dt-bindings: display: tegra: document Tegra20 and Tegra30 CSI Date: Tue, 19 Aug 2025 15:16:29 +0300 Message-ID: <20250819121631.84280-18-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819121631.84280-1-clamor95@gmail.com> References: <20250819121631.84280-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document CSI hw block found in Tegra20 and Tegra30 SoC. Signed-off-by: Svyatoslav Ryhel --- .../display/tegra/nvidia,tegra210-csi.yaml | 78 +++++++++++++++---- 1 file changed, 63 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra21= 0-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra21= 0-csi.yaml index fa07a40d1004..a5669447a33b 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.y= aml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.y= aml @@ -16,30 +16,78 @@ properties: =20 compatible: enum: + - nvidia,tegra20-csi + - nvidia,tegra30-csi - nvidia,tegra210-csi =20 reg: maxItems: 1 =20 - clocks: - items: - - description: module clock - - description: A/B lanes clock - - description: C/D lanes clock - - description: E lane clock - - description: test pattern generator clock - - clock-names: - items: - - const: csi - - const: cilab - - const: cilcd - - const: cile - - const: csi_tpg + clocks: true + clock-names: true =20 power-domains: maxItems: 1 =20 +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-csi + then: + properties: + clocks: + items: + - description: module clock + + clock-names: + items: + - const: csi + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra30-csi + then: + properties: + clocks: + items: + - description: module clock + - description: PAD A clock + - description: PAD B clock + + clock-names: + items: + - const: csi + - const: csia_pad + - const: csib_pad + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra210-csi + then: + properties: + clocks: + items: + - description: module clock + - description: A/B lanes clock + - description: C/D lanes clock + - description: E lane clock + - description: test pattern generator clock + + clock-names: + items: + - const: csi + - const: cilab + - const: cilcd + - const: cile + - const: csi_tpg + additionalProperties: false =20 required: --=20 2.48.1