.../bindings/phy/renesas,usb2-phy.yaml | 1 + .../reset/renesas,rzg2l-usbphy-ctrl.yaml | 41 +++++- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 118 ++++++++++++++++++ arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 57 +++++++++ drivers/phy/renesas/phy-rcar-gen3-usb2.c | 11 +- drivers/reset/Kconfig | 1 + drivers/reset/reset-rzg2l-usbphy-ctrl.c | 70 +++++++++++ 7 files changed, 292 insertions(+), 7 deletions(-)
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Hi,
Series adds initial USB support for the Renesas RZ/G3S SoC.
Series is split as follows:
- patches 1-2/7 - fixes on bindings and driver for USB PHY
- patches 3-5/7 - updates the rzg2l-usbphy-ctrl driver and documentation
with support for setting PWRRDY though SYSC
- patches 6-7/7 - add device tree support
Merge strategy, if any:
- patches 1-2/7 can go through the PHY tree
- patches 3-5/7 can go through the reset tree
- patches 6-7/7 can go through Renesas tree
Thank you,
Claudiu Beznea
Changes in v5:
- dropped patch "soc: renesas: rz-sysc: Add syscon/regmap support" as it
already modified and pubished also at [2] with the latest review comments
addressed
- fixed the documentation
Changes in v4:
- replaced "renesas,sysc-signals" DT property with "renesas,sysc-pwrrdy"
- dropped the "renesas,sysc-signals" property from USB PHY (as proposed
in v3) and let only the USB PHY CTRL driver to handle it as on RZ/G3S
the USB PHY CTRL driver needs to be probed before any other USB driver
- dropped the signal abstraction from SYSC driver as there is no need
for reference counting it now
- adjusted the "soc: renesas: rz-sysc: Add syscon/regmap support" to
comply with the latest review comments
Changes in v3:
- as the basics of the SYSC driver was integrated, only the signal support
was preserved in this series, in a separate patch; patch 01/12 was
adjusted (by addressing the review comments received at [1]) as it is
necessary to build the signal support on top of it
- after long discussions with the internal HW team it has been confirmed
that the relation b/w individual USB specific HW blocks and signals
is like:
┌──────────────────────────────┐
│ │◄── CPG_CLKON_USB.CLK0_ON
│ USB CH0 │
┌──────────────────────────┐ │┌───────────────────────────┐ │◄── CPG_CLKON_USB.CLK2_ON
│ ┌────────┐ ││host controller registers │ │
│ │ │ ││function controller registers│
│ │ PHY0 │◄──┤└───────────────────────────┘ │
│ USB PHY │ │ └────────────▲─────────────────┘
│ └────────┘ │
│ │ CPG_BUS_PERI_COM_MSTOP.MSTOP{6, 5}_ON
│┌──────────────┐ ┌────────┐
││USBPHY control│ │ │
││ registers │ │ PHY1 │ ┌──────────────────────────────┐
│└──────────────┘ │ │◄──┤ USB CH1 │
│ └────────┘ │┌───────────────────────────┐ │◄── CPG_CLKON_USB.CLK1_ON
└─▲───────▲─────────▲──────┘ ││ host controller registers │ │
│ │ │ │└───────────────────────────┘ │
│ │ │ └────────────▲─────────────────┘
│ │ │ │
│ │ │ CPG_BUS_PERI_COM_MSTOP.MSTOP7_ON
│PWRRDY │ │
│ │ CPG_CLK_ON_USB.CLK3_ON
│ │
│ CPG_BUS_PERI_COM_MSTOP.MSTOP4_ON
│
┌────┐
│SYSC│
└────┘
where:
- CPG_CLKON_USB.CLK.CLKX_ON is the register bit controlling the clock X
of different USB blocks, X in {0, 1, 2, 3}
- CPG_BUS_PERI_COM_MSTOP.MSTOPX_ON is the register bit controlling the
MSTOP of different USB blocks, X in {4, 5, 6, 7}
- USB PHY is the USB PHY block exposing 2 ports, port0 and port1, used
by the USB CH0, USB CH1
- SYSC is the system controller block controlling the PWRRDY signal
- USB CHx are individual USB block with host and function capabilities
(USB CH0 have both host and function capabilities, USB CH1 has only
host capabilities)
Due to this, the PWRRDY signal was also passed to the reset-rzg2l-usbphy-ctrl
reset driver (as it controls the USBPHY control registers) and these
are in the USB PHY block controlled by PWRRDY signal.
The PWRRDY signal need to be de-asserted on probe before enabling the module
clocks and the module MSTOP. To avoid any violation of this configuration
sequence, the PWRRDY signal is now controlled by USB PHY driver and the
reset-rzg2l-usbphy-ctrl driver.
As the PHYs gets reset signals from the USB reset controller driver, the
reset-rzg2l-usbphy-ctrl is probed before the USB PHY driver and thus,
in theory, we can drop the signal support (reference counting of the
USB PWRRDY) and configure the USB PWRRDY just in the reset-rzg2l-usbphy-ctrl.
However, to have a proper description of the diagram described above in
device tree and ensure the configuration sequence b/w PRWRDY, CLK and MSTOP
is preserved, the PWRRDY signal is controlled in this series in all the
drivers that work with registers from the USB PHY block.
Please provide your feedback on this solution.
Thank you,
Claudiu
[1] https://lore.kernel.org/all/20250330214945.185725-2-john.madieu.xa@bp.renesas.com/
[2] https://lore.kernel.org/all/20250818162859.9661-2-john.madieu.xa@bp.renesas.com/
Changes in v2:
- dropped v1 patches already applied
- added fixes patches (07/14 and 09/14)
- dropped the approach of handling the USB PWRRDY though a reset controller
driver and introduced the signal concept for the SYSC driver; because
of this, most of the work done in v1 was dropped
- per patch changes are listed in individual patches, if any
Christophe JAILLET (1):
phy: renesas: rcar-gen3-usb2: Fix an error handling path in
rcar_gen3_phy_usb2_probe()
Claudiu Beznea (6):
dt-bindings: phy: renesas,usb2-phy: Mark resets as required for RZ/G3S
dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support
reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY
reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC
arm64: dts: renesas: r9a08g045: Add USB support
arm64: dts: renesas: rzg3s-smarc: Enable USB support
.../bindings/phy/renesas,usb2-phy.yaml | 1 +
.../reset/renesas,rzg2l-usbphy-ctrl.yaml | 41 +++++-
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 118 ++++++++++++++++++
arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 57 +++++++++
drivers/phy/renesas/phy-rcar-gen3-usb2.c | 11 +-
drivers/reset/Kconfig | 1 +
drivers/reset/reset-rzg2l-usbphy-ctrl.c | 70 +++++++++++
7 files changed, 292 insertions(+), 7 deletions(-)
--
2.43.0
Hi Claudiu, > Series adds initial USB support for the Renesas RZ/G3S SoC. > > Series is split as follows: > - patches 1-2/7 - fixes on bindings and driver for USB PHY > - patches 3-5/7 - updates the rzg2l-usbphy-ctrl driver and documentation > with support for setting PWRRDY though SYSC > - patches 6-7/7 - add device tree support Can you kindly send me a working config (privately will do). I think I enabled all the necessary config options but still get: [ 0.271024] rzg2l_usbphy_ctrl 11e00000.usbphy-ctrl: probe with driver rzg2l_usbphy_ctrl failed with error -22 ... [ 10.981612] platform 11e20000.usb: deferred probe pending: platform: supplier 11e10200.usb-phy not ready [ 10.984103] platform 11e10200.usb-phy: deferred probe pending: platform: wait for supplier /soc/usbphy-ctrl@11e00000/regulator-vbus Thanks, Wolfram
Hi, Wolfram,
On 8/28/25 11:56, Wolfram Sang wrote:
> Hi Claudiu,
>
>> Series adds initial USB support for the Renesas RZ/G3S SoC.
>>
>> Series is split as follows:
>> - patches 1-2/7 - fixes on bindings and driver for USB PHY
>> - patches 3-5/7 - updates the rzg2l-usbphy-ctrl driver and documentation
>> with support for setting PWRRDY though SYSC
>> - patches 6-7/7 - add device tree support
>
> Can you kindly send me a working config (privately will do). I think I
> enabled all the necessary config options but still get:
>
> [ 0.271024] rzg2l_usbphy_ctrl 11e00000.usbphy-ctrl: probe with driver rzg2l_usbphy_ctrl failed with error -22
> ...
> [ 10.981612] platform 11e20000.usb: deferred probe pending: platform: supplier 11e10200.usb-phy not ready
> [ 10.984103] platform 11e10200.usb-phy: deferred probe pending: platform: wait for supplier /soc/usbphy-ctrl@11e00000/regulator-vbus
I just checked it on latest linux-next and all good on my side. Would it be
possible that you don't have commit 2da2740fb9c8 ("soc: renesas: rz-sysc: Add
syscon/regmap support") in your tree?
This is how my tree looks like:
1db69bbb9c49 (HEAD) arm64: dts: renesas: rzg3s-smarc: Enable USB support
ee93ed9f0097 arm64: dts: renesas: r9a08g045: Add USB support
285447f934f3 reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC
8c758908876c reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY
8e41c54ab567 dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support
02db7a65b4b3 phy: renesas: rcar-gen3-usb2: Fix an error handling path in
rcar_gen3_phy_usb2_probe()
217453b58bdf dt-bindings: phy: renesas,usb2-phy: Mark resets as required for RZ/G3S
0f4c93f7eb86 (tag: next-20250822, linux-next/master) Add linux-next specific
files for 20250822
and few checks on my board:
root@smarc-rzg3s:~# uname -r
6.17.0-rc2-next-20250822-00007-g1db69bbb9c49
root@smarc-rzg3s:~# [ 217.627804] usb 1-1.2: USB disconnect, device number 4
[ 217.627804] usb 1-1.2: USB disconnect, device number 4
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~# lsusb
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 001 Device 002: ID 045b:022b Hitachi, Ltd
Bus 001 Device 003: ID 8087:0029 Intel Corp. AX200 Bluetooth
Bus 002 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
Bus 003 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 004 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
root@smarc-rzg3s:~# [ 231.154575] usb 1-1.2: new high-speed USB device number 5
using ehci-platform
[ 231.154575] usb 1-1.2: new high-speed USB device number 5 using ehci-platform
[ 231.299629] usb-storage 1-1.2:1.0: USB Mass Storage device detected
[ 231.299629] usb-storage 1-1.2:1.0: USB Mass Storage device detected
[ 231.327087] scsi host0: usb-storage 1-1.2:1.0
[ 231.327087] scsi host0: usb-storage 1-1.2:1.0
[ 232.348676] scsi 0:0:0:0: Direct-Access SanDisk Cruzer Blade 1.00
PQ: 0 ANSI: 6
[ 232.348676] scsi 0:0:0:0: Direct-Access SanDisk Cruzer Blade 1.00
PQ: 0 ANSI: 6
[ 232.382829] sd 0:0:0:0: [sda] 31260672 512-byte logical blocks: (16.0 GB/14.9
GiB)
[ 232.382829] sd 0:0:0:0: [sda] 31260672 512-byte logical blocks: (16.0 GB/14.9
GiB)
[ 232.417118] sd 0:0:0:0: [sda] Write Protect is off
[ 232.417118] sd 0:0:0:0: [sda] Write Protect is off
[ 232.430023] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled,
doesn't support DPO or FUA
[ 232.430023] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled,
doesn't support DPO or FUA
[ 232.481535] sda: sda1
[ 232.481535] sda: sda1
[ 232.490719] sd 0:0:0:0: [sda] Attached SCSI removable disk
[ 232.490719] sd 0:0:0:0: [sda] Attached SCSI removable disk
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~# lsusb
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 001 Device 002: ID 045b:022b Hitachi, Ltd
Bus 001 Device 003: ID 8087:0029 Intel Corp. AX200 Bluetooth
Bus 001 Device 005: ID 0781:5567 SanDisk Corp. Cruzer Blade
Bus 002 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
Bus 003 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 004 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
Thank you for looking to this,
Claudiu
>
> Thanks,
>
> Wolfram
>
Hi Claudiu,
> I just checked it on latest linux-next and all good on my side. Would it be
> possible that you don't have commit 2da2740fb9c8 ("soc: renesas: rz-sysc:
> Add syscon/regmap support") in your tree?
Yes, I added it and it made the error go away, but still no USB. I
switched to linux-next as of today, did neither help.
> This is how my tree looks like:
Mine is similar, except for a newer -next.
Let's try your config file next?
Thanks for the support,
Wolfram
Hi, Wolfram,
On 8/29/25 13:53, Wolfram Sang wrote:
> Hi Claudiu,
>
>> I just checked it on latest linux-next and all good on my side. Would it be
>> possible that you don't have commit 2da2740fb9c8 ("soc: renesas: rz-sysc:
>> Add syscon/regmap support") in your tree?
>
> Yes, I added it and it made the error go away, but still no USB. I
The drivers are not probed or you see no activity when connecting USB devices?
> switched to linux-next as of today, did neither help.
>
>> This is how my tree looks like:
>
> Mine is similar, except for a newer -next.
>
> Let's try your config file next?
I used arm64 defconfig (arch/arm64/configs/defconfig).
Thank you,
Claudiu
> > Yes, I added it and it made the error go away, but still no USB. I > > The drivers are not probed or you see no activity when connecting USB devices? Sigh, I was so sure to have checked OHCI/EHCI but only EHCI was enabled :( Checking with the schematics, I get it that only the rightmost USB-A connectors on the carrier board are routed. Those two work fine now. If that is to be expected, then for the whole series: Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
On 8/29/25 14:51, Wolfram Sang wrote: > >>> Yes, I added it and it made the error go away, but still no USB. I >> >> The drivers are not probed or you see no activity when connecting USB devices? > > Sigh, I was so sure to have checked OHCI/EHCI but only EHCI was enabled :( > > Checking with the schematics, I get it that only the rightmost USB-A > connectors on the carrier board are routed. Those two work fine now. > > If that is to be expected, then for the whole series: Yes, only those 2 are routed on RZ SMARC Carrier II + RZ/G3S SMARC Module. > > Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > Thank you for doing this, Claudiu
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