A couple of registers of the system controller (sys) are shared with the TSU
device. Add #address-cells property to sys node to allow proper parsing a
access to these registers from the TSU driver.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---

Changes:
 - v7: new patch: as sys specifier has changed for TSU node, add this patch
 to specify #address-cells.

 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index e4fac7e0d764..7cbba492edd5 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -278,6 +278,7 @@ sys: system-controller@10430000 {
 			reg = <0 0x10430000 0 0x10000>;
 			clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>;
 			resets = <&cpg 0x30>;
+			#address-cells = <1>;
 		};
 
 		xspi: spi@11030000 {
-- 
2.25.1

Hi John,

On Mon, 18 Aug 2025 at 18:29, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> A couple of registers of the system controller (sys) are shared with the TSU
> device. Add #address-cells property to sys node to allow proper parsing a
> access to these registers from the TSU driver.
>
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> @@ -278,6 +278,7 @@ sys: system-controller@10430000 {
>                         reg = <0 0x10430000 0 0x10000>;
>                         clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>;
>                         resets = <&cpg 0x30>;
> +                       #address-cells = <1>;

Iff you need this, you need to update the DT bindings first, as reported
by Rob's bot.

However, looking at Claudiu's USB series [1], I think you can do
without, by calling of_parse_phandle_with_fixed_args() instead of
of_parse_phandle_with_args() in the driver.

>                 };
>
>                 xspi: spi@11030000 {

[1] "[PATCH v5 0/7] Add initial USB support for the Renesas RZ/G3S SoC"
    https://lore.kernel.org/20250819054212.486426-1-claudiu.beznea.uj@bp.renesas.com

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds