The Motorcomm YT921x series is a family of Ethernet switches with up to
8 internal GbE PHYs and up to 2 GMACs.
Signed-off-by: David Yang <mmyangfl@gmail.com>
---
.../bindings/net/dsa/motorcomm,yt921x.yaml | 162 ++++++++++++++++++
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@@ -0,0 +1,162 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/motorcomm,yt921x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Motorcomm YT921x Ethernet switch family
+
+maintainers:
+ - David Yang <mmyangfl@gmail.com>
+
+description: |
+ The Motorcomm YT921x series is a family of Ethernet switches with up to 8
+ internal GbE PHYs and up to 2 GMACs, including:
+
+ - YT9215S / YT9215RB / YT9215SC: 5 GbE PHYs (Port 0-4) + 2 GMACs (Port 8-9)
+ - YT9213NB: 2 GbE PHYs (Port 1/3) + 1 GMAC (Port 9)
+ - YT9214NB: 2 GbE PHYs (Port 1/3) + 2 GMACs (Port 8-9)
+ - YT9218N: 8 GbE PHYs (Port 0-7)
+ - YT9218MB: 8 GbE PHYs (Port 0-7) + 2 GMACs (Port 8-9)
+
+ Any port can be used as the CPU port.
+
+properties:
+ compatible:
+ const: motorcomm,yt9215
+
+ reg:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+
+ motorcomm,switch-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Value selected by Pin SWITCH_ID_1 / SWITCH_ID_0.
+
+ Up to 4 chips can share the same MII port ('reg' in DT) by giving
+ different SWITCH_ID values. The default value should work if only one chip
+ is present.
+ enum: [0, 1, 2, 3]
+ default: 0
+
+ mdio:
+ $ref: /schemas/net/mdio.yaml#
+ unevaluatedProperties: false
+ description: |
+ Internal MDIO bus for the internal GbE PHYs. PHYs 0-7 are used for Port
+ 0-7 respectively.
+
+ mdio-external:
+ $ref: /schemas/net/mdio.yaml#
+ unevaluatedProperties: false
+ description: |
+ External MDIO bus to access external components. External PHYs for GMACs
+ (Port 8-9) are expected to be connected to the external MDIO bus in
+ vendor's reference design, but that is not a hard limitation from the
+ chip.
+
+allOf:
+ - $ref: dsa.yaml#/$defs/ethernet-ports
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch@1d {
+ compatible = "motorcomm,yt9215";
+ /* default 0x1d, alternate 0x0 */
+ reg = <0x1d>;
+ motorcomm,switch-id = <0>;
+ reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sw_phy0: phy@0 {
+ reg = <0x0>;
+ };
+ };
+
+ mdio-external {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy1: phy@b {
+ reg = <0xb>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* phy-handle is optional for internal PHYs */
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ phy-mode = "internal";
+ phy-handle = <&sw_phy0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ phy-mode = "internal";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ phy-mode = "internal";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ phy-mode = "internal";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan5";
+ phy-mode = "internal";
+ };
+
+ /* CPU port */
+ port@8 {
+ reg = <8>;
+ phy-mode = "sgmii";
+ ethernet = <ð0>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ asym-pause;
+ };
+ };
+
+ /* if external phy is connected to a MAC */
+ port@9 {
+ reg = <9>;
+ label = "wan";
+ phy-mode = "rgmii";
+ phy-handle = <&phy1>;
+ };
+ };
+ };
+ };
--
2.50.1> + motorcomm,switch-id:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + Value selected by Pin SWITCH_ID_1 / SWITCH_ID_0.
> +
> + Up to 4 chips can share the same MII port ('reg' in DT) by giving
> + different SWITCH_ID values. The default value should work if only one chip
> + is present.
> + enum: [0, 1, 2, 3]
> + default: 0
It is like getting blood from a stone.
So what you are saying is that you have:
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch@1d {
compatible = "motorcomm,yt9215";
/* default 0x1d, alternate 0x0 */
reg = <0x1d>;
motorcomm,switch-id = <0>;
reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
...
}
switch@1d {
compatible = "motorcomm,yt9215";
reg = <0x1d>;
motorcomm,switch-id = <1>;
reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
...
}
switch@1d {
compatible = "motorcomm,yt9215";
reg = <0x1d>;
motorcomm,switch-id = <2>;
reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
...
}
}
Have you tested this? My _guess_ is, it does not work.
I'm not even sure DT allows you to have the same reg multiple times on
one bus.
I'm pretty sure the MDIO core does not allow multiple devices on one
MDIO address. Each device is represented by a struct
mdio_device. struct mii_bus has an array of 32 of these, one per
address on the bus. You cannot have 4 of them for one address.
Andrew
---
pw-bot: cr
On 18/08/2025 18:55, Andrew Lunn wrote:
>> + motorcomm,switch-id:
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + description: |
>> + Value selected by Pin SWITCH_ID_1 / SWITCH_ID_0.
>> +
>> + Up to 4 chips can share the same MII port ('reg' in DT) by giving
>> + different SWITCH_ID values. The default value should work if only one chip
>> + is present.
>> + enum: [0, 1, 2, 3]
>> + default: 0
>
> It is like getting blood from a stone.
>
> So what you are saying is that you have:
>
> mdio {
> #address-cells = <1>;
> #size-cells = <0>;
>
> switch@1d {
> compatible = "motorcomm,yt9215";
> /* default 0x1d, alternate 0x0 */
> reg = <0x1d>;
> motorcomm,switch-id = <0>;
> reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
> ...
> }
>
> switch@1d {
> compatible = "motorcomm,yt9215";
> reg = <0x1d>;
> motorcomm,switch-id = <1>;
> reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
> ...
> }
>
> switch@1d {
> compatible = "motorcomm,yt9215";
> reg = <0x1d>;
> motorcomm,switch-id = <2>;
> reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
> ...
> }
> }
>
> Have you tested this? My _guess_ is, it does not work.
Regardless if kernel actually works with this, but duplicating unit
address is not supported, so this obviously would be wrong. I guess
that's the answer for switch-id.
Best regards,
Krzysztof
On Tue, Aug 19, 2025 at 12:55 AM Andrew Lunn <andrew@lunn.ch> wrote:
>
> > + motorcomm,switch-id:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description: |
> > + Value selected by Pin SWITCH_ID_1 / SWITCH_ID_0.
> > +
> > + Up to 4 chips can share the same MII port ('reg' in DT) by giving
> > + different SWITCH_ID values. The default value should work if only one chip
> > + is present.
> > + enum: [0, 1, 2, 3]
> > + default: 0
>
> It is like getting blood from a stone.
>
> So what you are saying is that you have:
>
> mdio {
> #address-cells = <1>;
> #size-cells = <0>;
>
> switch@1d {
> compatible = "motorcomm,yt9215";
> /* default 0x1d, alternate 0x0 */
> reg = <0x1d>;
> motorcomm,switch-id = <0>;
> reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
> ...
> }
>
> switch@1d {
> compatible = "motorcomm,yt9215";
> reg = <0x1d>;
> motorcomm,switch-id = <1>;
> reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
> ...
> }
>
> switch@1d {
> compatible = "motorcomm,yt9215";
> reg = <0x1d>;
> motorcomm,switch-id = <2>;
> reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
> ...
> }
> }
>
> Have you tested this? My _guess_ is, it does not work.
>
> I'm not even sure DT allows you to have the same reg multiple times on
> one bus.
>
> I'm pretty sure the MDIO core does not allow multiple devices on one
> MDIO address. Each device is represented by a struct
> mdio_device. struct mii_bus has an array of 32 of these, one per
> address on the bus. You cannot have 4 of them for one address.
>
> Andrew
>
> ---
> pw-bot: cr
Of course I cannot test this, since I only have a stock device, as
mentioned in patch 3.
But I think this is what the vendor wants to do, if I got it right
from the datasheet.
If this is not acceptable anyway, I might as well remove switch-id
completely since I doubt if anyone would concat more than one switch
together in real world.
On Tue, Aug 19, 2025 at 01:06:00AM +0800, Yangfl wrote:
> On Tue, Aug 19, 2025 at 12:55 AM Andrew Lunn <andrew@lunn.ch> wrote:
> >
> > > + motorcomm,switch-id:
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + description: |
> > > + Value selected by Pin SWITCH_ID_1 / SWITCH_ID_0.
> > > +
> > > + Up to 4 chips can share the same MII port ('reg' in DT) by giving
> > > + different SWITCH_ID values. The default value should work if only one chip
> > > + is present.
> > > + enum: [0, 1, 2, 3]
> > > + default: 0
> >
> > It is like getting blood from a stone.
> >
> > So what you are saying is that you have:
> >
> > mdio {
> > #address-cells = <1>;
> > #size-cells = <0>;
> >
> > switch@1d {
> > compatible = "motorcomm,yt9215";
> > /* default 0x1d, alternate 0x0 */
> > reg = <0x1d>;
> > motorcomm,switch-id = <0>;
> > reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
> > ...
> > }
> >
> > switch@1d {
> > compatible = "motorcomm,yt9215";
> > reg = <0x1d>;
> > motorcomm,switch-id = <1>;
> > reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
> > ...
> > }
> >
> > switch@1d {
> > compatible = "motorcomm,yt9215";
> > reg = <0x1d>;
> > motorcomm,switch-id = <2>;
> > reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
> > ...
> > }
> > }
> >
> > Have you tested this? My _guess_ is, it does not work.
> >
> > I'm not even sure DT allows you to have the same reg multiple times on
> > one bus.
> >
> > I'm pretty sure the MDIO core does not allow multiple devices on one
> > MDIO address. Each device is represented by a struct
> > mdio_device. struct mii_bus has an array of 32 of these, one per
> > address on the bus. You cannot have 4 of them for one address.
> >
> > Andrew
> >
> > ---
> > pw-bot: cr
>
> Of course I cannot test this, since I only have a stock device, as
> mentioned in patch 3.
You could create such a DT and see if it compiles and passes the
binding tests. You could boot such a DT. You should get -ENODEV for
the other two devices. But if it crashes, that tells you
something... Looking at the stack trace might confirm this is never
going to work with the current MDIO core code.
> If this is not acceptable anyway, I might as well remove switch-id
> completely since I doubt if anyone would concat more than one switch
> together in real world.
I have a board with 4 Marvell switches. It does happen, especially in
industrial systems. But they have individual addresses on the MDIO
bus. I also have a SOHO black box switch, using two qualcomm switches
in order to support 16 ports.
But i do agree you are unlikely to see a WiFi AP, or a cable modem use
two switches.
Andrew
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