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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Russell King , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next v4 1/3] dt-bindings: net: dsa: yt921x: Add Motorcomm YT921x switch support Date: Tue, 19 Aug 2025 00:24:40 +0800 Message-ID: <20250818162445.1317670-2-mmyangfl@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250818162445.1317670-1-mmyangfl@gmail.com> References: <20250818162445.1317670-1-mmyangfl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Motorcomm YT921x series is a family of Ethernet switches with up to 8 internal GbE PHYs and up to 2 GMACs. Signed-off-by: David Yang --- .../bindings/net/dsa/motorcomm,yt921x.yaml | 162 ++++++++++++++++++ 1 file changed, 162 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dsa/motorcomm,yt9= 21x.yaml diff --git a/Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yam= l b/Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml new file mode 100644 index 000000000000..f7c05eaf0038 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/motorcomm,yt921x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Motorcomm YT921x Ethernet switch family + +maintainers: + - David Yang + +description: | + The Motorcomm YT921x series is a family of Ethernet switches with up to 8 + internal GbE PHYs and up to 2 GMACs, including: + + - YT9215S / YT9215RB / YT9215SC: 5 GbE PHYs (Port 0-4) + 2 GMACs (Port= 8-9) + - YT9213NB: 2 GbE PHYs (Port 1/3) + 1 GMAC (Port 9) + - YT9214NB: 2 GbE PHYs (Port 1/3) + 2 GMACs (Port 8-9) + - YT9218N: 8 GbE PHYs (Port 0-7) + - YT9218MB: 8 GbE PHYs (Port 0-7) + 2 GMACs (Port 8-9) + + Any port can be used as the CPU port. + +properties: + compatible: + const: motorcomm,yt9215 + + reg: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + motorcomm,switch-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Value selected by Pin SWITCH_ID_1 / SWITCH_ID_0. + + Up to 4 chips can share the same MII port ('reg' in DT) by giving + different SWITCH_ID values. The default value should work if only on= e chip + is present. + enum: [0, 1, 2, 3] + default: 0 + + mdio: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + description: | + Internal MDIO bus for the internal GbE PHYs. PHYs 0-7 are used for P= ort + 0-7 respectively. + + mdio-external: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + description: | + External MDIO bus to access external components. External PHYs for G= MACs + (Port 8-9) are expected to be connected to the external MDIO bus in + vendor's reference design, but that is not a hard limitation from the + chip. + +allOf: + - $ref: dsa.yaml#/$defs/ethernet-ports + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + switch@1d { + compatible =3D "motorcomm,yt9215"; + /* default 0x1d, alternate 0x0 */ + reg =3D <0x1d>; + motorcomm,switch-id =3D <0>; + reset-gpios =3D <&tlmm 39 GPIO_ACTIVE_LOW>; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + sw_phy0: phy@0 { + reg =3D <0x0>; + }; + }; + + mdio-external { + #address-cells =3D <1>; + #size-cells =3D <0>; + + phy1: phy@b { + reg =3D <0xb>; + }; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* phy-handle is optional for internal PHYs */ + port@0 { + reg =3D <0>; + label =3D "lan1"; + phy-mode =3D "internal"; + phy-handle =3D <&sw_phy0>; + }; + + port@1 { + reg =3D <1>; + label =3D "lan2"; + phy-mode =3D "internal"; + }; + + port@2 { + reg =3D <2>; + label =3D "lan3"; + phy-mode =3D "internal"; + }; + + port@3 { + reg =3D <3>; + label =3D "lan4"; + phy-mode =3D "internal"; + }; + + port@4 { + reg =3D <4>; + label =3D "lan5"; + phy-mode =3D "internal"; + }; + + /* CPU port */ + port@8 { + reg =3D <8>; + phy-mode =3D "sgmii"; + ethernet =3D <ð0>; + + fixed-link { + speed =3D <1000>; + full-duplex; + pause; + asym-pause; + }; + }; + + /* if external phy is connected to a MAC */ + port@9 { + reg =3D <9>; + label =3D "wan"; + phy-mode =3D "rgmii"; + phy-handle =3D <&phy1>; + }; + }; + }; + }; --=20 2.50.1