[v1] Properly Limit Tegra210 Clock Rates

[PATCH 0/5] Properly Limit Tegra210 Clock Rates

Aaron Kling via B4 Relay posted 5 patches 1 month, 2 weeks ago

Diff against v2
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There is a newer version of this series

.../bindings/clock/nvidia,tegra124-dfll.txt        |  3 ++
arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts |  1 +
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c         |  8 ++++-
drivers/soc/tegra/fuse/speedo-tegra210.c           | 39 ++++++++++++++++++----
4 files changed, 43 insertions(+), 8 deletions(-)

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[PATCH 0/5] Properly Limit Tegra210 Clock Rates

Posted by Aaron Kling via B4 Relay 1 month, 2 weeks ago

The Tegra210 CVB tables were added in commit 2b2dbc2f94e5. Since then,
all Tegra210 socs have tried to scale the cpu to 1.9 GHz, when the
supported devkits are only supposed to scale to 1.5 or 1.7 GHZ.
Overclocking should not be the default state.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
Aaron Kling (5):
      dt-bindings: clock: tegra124-dfll: Add property to limit frequency
      soc: tegra: fuse: speedo-tegra210: Update speedo ids
      soc: tegra: fuse: speedo-tegra210: Add sku 0x8F
      clk: tegra: dfll: Support limiting max clock per device
      arm64: tegra: Limit max cpu frequency on P3450

 .../bindings/clock/nvidia,tegra124-dfll.txt        |  3 ++
 arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts |  1 +
 drivers/clk/tegra/clk-tegra124-dfll-fcpu.c         |  8 ++++-
 drivers/soc/tegra/fuse/speedo-tegra210.c           | 39 ++++++++++++++++++----
 4 files changed, 43 insertions(+), 8 deletions(-)
---
base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585
change-id: 20250812-tegra210-speedo-470691e8b8cc

Best regards,
-- 
Aaron Kling <webgeek1234@gmail.com>