From nobody Sat Oct 4 12:41:17 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C84AFBF0; Sat, 16 Aug 2025 05:54:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755323659; cv=none; b=TeGvolFndQpodp/UBaM4Rj+ujQLAAq6fCyCf3a5r08an5fP1aXZIU2VDVh7P06sDHkLSi6TslW3CftUmcO0f2YhzC4/qv40LVpQfIdKNOaeb7guni9efbUHgWZzE32Ydlizp2+NdhdrIG/rP3p4D9KtkYc4wdUG1klJxhsx2Peg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755323659; c=relaxed/simple; bh=cOotQfb3hXrw4Cc4Ozk3KZs+QDC0iDdLyslVoGta5QQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KuWYlBaEvuTCtx0Ht8MU8562P2a5vg/zKXAyJyN14E8t0BlmJpvz/He8l0RHnVCY8BPujaHRJ4rSfdOqt4RK0TfroNDM44r+XRTe/AoIRS6kffOfSFfo4hCc6/QcXEJgYrFmV2H1Nq3jaxkk+BBiJv+sW+ergpguCXLWGRNCoKU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=evScQ224; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="evScQ224" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0C25DC4CEF5; Sat, 16 Aug 2025 05:54:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755323659; bh=cOotQfb3hXrw4Cc4Ozk3KZs+QDC0iDdLyslVoGta5QQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=evScQ2246WRm+K6XcJD7i8B6eT/naoG2Fr7u7kYeiquxX5KLsK5q9cbnxIvNaVi1d E9EXOwKEsjaxrIblZHRx9o5jcqNGZNaO7goupJwfXSMP5FFrhfckeykqndcFMKdPHZ ROLeBh//6NnPXrji7ZoSu/kXl6e08IAWBC/Ce9z2FpaiMyWR7thikpyN3R0Qvh5x+M V+IgTY6UoiOC6lINfsu/DQjvpstdd7G8cSh9gkqxSpIep3jdL6S9qDBSldFP0QTXqe CMhc4e68jF9j5ivlPvPwFAQG1AmpwbMgzXTd+y3mrD+q8XjqDjfIPQR3hnfVTIkgDQ eJ7RviHAUZXrA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0C86CA0EE6; Sat, 16 Aug 2025 05:54:18 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Sat, 16 Aug 2025 00:53:33 -0500 Subject: [PATCH 1/5] dt-bindings: clock: tegra124-dfll: Add property to limit frequency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250816-tegra210-speedo-v1-1-a981360adc27@gmail.com> References: <20250816-tegra210-speedo-v1-0-a981360adc27@gmail.com> In-Reply-To: <20250816-tegra210-speedo-v1-0-a981360adc27@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Joseph Lo , Peter De Schrijver , Prashant Gaikwad Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Thierry Reding , Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755323658; l=1074; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=i008IfPSaYeZDCxQCAJ7fiLJ8vYgRkhMPyZzDoavqYE=; b=RsGAR4X/ZLdBD17nQiWJrjizisf+BJBjuFoEXnTzahSr2JDZ4hFiMsowb5/xLuAlDn6sOrX9X gmronvaJJWgAovoTwAAj/SWd+3XthQrlMvT1oUzBKVEHfVcnNjjYmMI X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Some devices report a cpu speedo value that corresponds to a table that scales beyond the chips capability. This allows devices to set a lower limit. Signed-off-by: Aaron Kling --- Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.t= xt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt index f7d347385b5775ddd702ecbb9821acfc9d4b9ff2..6cdbabc1f036a767bdc8e5df64e= eff34171a3b85 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt @@ -70,6 +70,9 @@ Required properties for PWM mode: - dvfs_pwm_enable: I/O pad configuration when PWM control is enabled. - dvfs_pwm_disable: I/O pad configuration when PWM control is disabled. =20 +Optional properties for limiting frequency: +- nvidia,dfll-max-freq: Maximum scaling frequency. + Example for I2C: =20 clock@70110000 { --=20 2.50.1 From nobody Sat Oct 4 12:41:17 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D97F78F29; Sat, 16 Aug 2025 05:54:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755323659; cv=none; b=P8w0yAEBapIxJJwVVLUPaZ075PvyC/7YqotEoOV2C1IqvDhyhpJq43Jx85btycwnllEHSqkStkDoTVV23pH0seRECqFhpZAJQj0f6jfCmk878coqZHdv3Dgcua6cBkl0g+yEMrWFUAiIZ6hhFpIG9XnybYcrKSt8S6BypKs9xSM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755323659; c=relaxed/simple; bh=QE0pcmBxzdI0WjlVdkCZ/0cBS345nxWSHXpkdIVR0XE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IRAs3q9E8sYYnIBr+ee2kDueWjMdE91Esa77s+vkOI3kE3Fr1Su+zuNHKEYxLe4f/nr7WsqaKq1WxwgM7mCkQmiXCjX5dhD/vx134I6T7bgQo0/03ntNXBzOivlevf4O39yqmBuViPnVbQ2YQp48qVvY7U5Mn4Bld/r72tAIfAo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PNDi3tnD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PNDi3tnD" Received: by smtp.kernel.org (Postfix) with ESMTPS id 19403C4CEF0; Sat, 16 Aug 2025 05:54:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755323659; bh=QE0pcmBxzdI0WjlVdkCZ/0cBS345nxWSHXpkdIVR0XE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=PNDi3tnDp0XMqWDJphnsqasqpOY8dEjbK0mdZ3qudV1oD1+H/TJg6wGtuqVL/fNyB PzWaQRa05N9jNfvbtnz4JyKh4IpntybyC+oKQUMj77jUGSANX4aIB/nKfJJFVoKh0Y 6zQM4iqD58BxWwjuDcZAhRk29XJVHALb/9/F1W4v9L5cHyP5lP9jqDCtDBZXxzgR30 CEltdp7vWD9jE3scnZ+hRmDrUPv2FQeGEv7w3lMFJJ8n+rdle+wOP+fyAJpgsZlx6+ yifF5XQeQYAv5n5vVf+/PacoUhehaLChrkxUCNZf/RAxAH7kNfxWfxdXblrX92dKu+ C+Up749h3wrxw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0ADAFCA0EE4; Sat, 16 Aug 2025 05:54:19 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Sat, 16 Aug 2025 00:53:34 -0500 Subject: [PATCH 2/5] soc: tegra: fuse: speedo-tegra210: Update speedo ids Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250816-tegra210-speedo-v1-2-a981360adc27@gmail.com> References: <20250816-tegra210-speedo-v1-0-a981360adc27@gmail.com> In-Reply-To: <20250816-tegra210-speedo-v1-0-a981360adc27@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Joseph Lo , Peter De Schrijver , Prashant Gaikwad Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Thierry Reding , Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755323658; l=1990; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=FEiuagoxyTly3FkCZVL5wqa+8cOCwUCmjC0lzQx+w7w=; b=He3TG2PtmZCXHlF7vNxNDd4ritkc368+eli+M7ceaJvNhMkyryYHofbSbs/lLbu3e6VEcTFhK oOx+R0gWx8rAbvXyanPZldRElXAfN3VzN2fgFJ7pM4L+rqPGe21N4Tw X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Existing code only sets cpu and gpu speedo ids 0 and 1. The cpu dvfs code supports 11 ids and nouveau supports 5. This aligns with what the downstream vendor kernel supports. Align the existing supported skus with the downstream speedo list. The Tegra210 CVB tables were added in the referenced fixes commit. Since then, all Tegra210 socs have tried to scale to 1.9 GHz, when the supported devkits are only supposed to scale to 1.5 or 1.7 GHZ. Overclocking should not be the default state. Fixes: 2b2dbc2f94e5 ("clk: tegra: dfll: add CVB tables for Tegra210") Signed-off-by: Aaron Kling --- drivers/soc/tegra/fuse/speedo-tegra210.c | 31 ++++++++++++++++++++++++----= --- 1 file changed, 24 insertions(+), 7 deletions(-) diff --git a/drivers/soc/tegra/fuse/speedo-tegra210.c b/drivers/soc/tegra/f= use/speedo-tegra210.c index 695d0b7f9a8abe53c497155603147420cda40b63..909fdf8fcc9d9f5ac936ae322e7= a73dc720e5ab6 100644 --- a/drivers/soc/tegra/fuse/speedo-tegra210.c +++ b/drivers/soc/tegra/fuse/speedo-tegra210.c @@ -68,18 +68,35 @@ static void __init rev_sku_to_speedo_ids(struct tegra_s= ku_info *sku_info, switch (sku) { case 0x00: /* Engineering SKU */ case 0x01: /* Engineering SKU */ + case 0x13: + if (speedo_rev >=3D 2) { + sku_info->cpu_speedo_id =3D 5; + sku_info->gpu_speedo_id =3D 2; + break; + } + + sku_info->gpu_speedo_id =3D 1; + break; + case 0x07: case 0x17: - case 0x27: - if (speedo_rev >=3D 2) - sku_info->gpu_speedo_id =3D 1; + if (speedo_rev >=3D 2) { + sku_info->cpu_speedo_id =3D 7; + sku_info->gpu_speedo_id =3D 2; + break; + } + + sku_info->gpu_speedo_id =3D 1; break; =20 - case 0x13: - if (speedo_rev >=3D 2) - sku_info->gpu_speedo_id =3D 1; + case 0x27: + if (speedo_rev >=3D 2) { + sku_info->cpu_speedo_id =3D 1; + sku_info->gpu_speedo_id =3D 2; + break; + } =20 - sku_info->cpu_speedo_id =3D 1; + sku_info->gpu_speedo_id =3D 1; break; =20 default: --=20 2.50.1 From nobody Sat Oct 4 12:41:17 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 735BC1F3BA4; Sat, 16 Aug 2025 05:54:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755323659; cv=none; b=XIx/x+bV0iSbl7GByRRU7uwB+HOgzav23qZgXxbo9HgICqlMYxWvdsxKwqBPMxrWH/DFDutYMa0VIYU9aFV1jNszUwoSEKSD8NeAZ1NIGvvr3AodTJe1cfEnjATzv11O63pN4ZtoWz920gTpA+Wx7jDx/KBloIr2xjfXSZqQUko= ARC-Message-Signature: i=1; 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b=a6+TDVppuLfi1C80sUnKDDoOQTXF0LMKB2s3TLmiV6osTmB/FoUMmurlvekkEaBJO IyhtVqiE30EfE9CUBkWSP+l5jiXcj3UactIJKqHmg1hxzyXrWNLBwbo0VmG+WNcrMx zPYQ+ptpK4/dBiqsKO8uglHN0ZMn/qZlcrK/qspIQNcU5VzJhFCwNjzqIw512aOeV4 gFhQjr7P0sNbLhbq+pCksu9LcGiPWOeD9G/PilccTCRlGCYki/kLIQK7Z+03BvasR9 Wteotm572S7Sxuqk7l6Obdc+2RMRFwmzrGC1WSd73TitC0OwrpGRrEfrgDBsF+O//l dBIAAHvK/Kzjw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18034CA0EEB; Sat, 16 Aug 2025 05:54:19 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Sat, 16 Aug 2025 00:53:35 -0500 Subject: [PATCH 3/5] soc: tegra: fuse: speedo-tegra210: Add sku 0x8F Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250816-tegra210-speedo-v1-3-a981360adc27@gmail.com> References: <20250816-tegra210-speedo-v1-0-a981360adc27@gmail.com> In-Reply-To: <20250816-tegra210-speedo-v1-0-a981360adc27@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Joseph Lo , Peter De Schrijver , Prashant Gaikwad Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Thierry Reding , Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755323658; l=976; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=pWQFdNwG5wqAUfrAYFEYhFd3g2VQZFhe1CBj1AG4N/Q=; b=hIQ9qJnm6qDoO0yAW2MX7dJ374+oXSQkdsje8YbYZoXPkHMerXkpgbxMnshwM0GU9PBkgI/FV +Z4KGZDvD4WAS1Ei5l804K8fZ1T7uKGLAjZhSgq6U1WrRdUaGAJbSxB X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling This is used by the Jetson Nano series of SoMs Fixes: 579db6e5d9b8 ("arm64: tegra: Enable DFLL support on Jetson Nano") Signed-off-by: Aaron Kling --- drivers/soc/tegra/fuse/speedo-tegra210.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/soc/tegra/fuse/speedo-tegra210.c b/drivers/soc/tegra/f= use/speedo-tegra210.c index 909fdf8fcc9d9f5ac936ae322e7a73dc720e5ab6..1cdd70c59c0753e602709f9179c= 0ab67d1b8f5e3 100644 --- a/drivers/soc/tegra/fuse/speedo-tegra210.c +++ b/drivers/soc/tegra/fuse/speedo-tegra210.c @@ -99,6 +99,14 @@ static void __init rev_sku_to_speedo_ids(struct tegra_sk= u_info *sku_info, sku_info->gpu_speedo_id =3D 1; break; =20 + case 0x8F: + if (speedo_rev >=3D 2) { + sku_info->cpu_speedo_id =3D 9; + sku_info->gpu_speedo_id =3D 2; + break; + } + fallthrough; + default: pr_err("Tegra210: unknown SKU %#04x\n", sku); /* Using the default for the error case */ --=20 2.50.1 From nobody Sat Oct 4 12:41:17 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 736131F4168; Sat, 16 Aug 2025 05:54:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755323659; cv=none; b=qO34zxekJsuNJEwB17ZanO4oT05ijtKhiOYBRC2/YKgHf4He1LYj9eJcZqM584G6uQhbH5M8CB3c6U5WRknkIf1ok9+XIlbG6WK0EQZl3THjc4HB0ixFbXG6nMQHxZ9zg7dcdx4QgcbfGmHdL8Qt+7Txtv4b7wZj2UPhle1v8KY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Sat, 16 Aug 2025 05:54:19 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Sat, 16 Aug 2025 00:53:36 -0500 Subject: [PATCH 4/5] clk: tegra: dfll: Support limiting max clock per device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250816-tegra210-speedo-v1-4-a981360adc27@gmail.com> References: <20250816-tegra210-speedo-v1-0-a981360adc27@gmail.com> In-Reply-To: <20250816-tegra210-speedo-v1-0-a981360adc27@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Joseph Lo , Peter De Schrijver , Prashant Gaikwad Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Thierry Reding , Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755323658; l=1449; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=F+yoRA15M31xbQIkPC6+4/poN2QJpx1PWxc/bXVO320=; b=sTV9RkNktfketMdtjuEkak8xkFZnoPszZGHh0v811QDSMTwmDGvJcopPKY1LzaYtIHzfBNHjB hRnt+C6cfP4AOceWHEFlJfKImaM+xDoRl0w16UCBz4iG2j9tBImXSRL X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Some devices like the Jetson Nano report a cpu speedo value that scales past the capabilities of the cpu. This allows limiting the maximum scaling to a lower value within the table. Signed-off-by: Aaron Kling --- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra= /clk-tegra124-dfll-fcpu.c index 0251618b82c8321724ba0aec7a5bd90b2c2ffaf2..0c84f7e85baaa96fee005a1c9a5= dd6afbd1875fa 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -556,6 +556,7 @@ static int tegra124_dfll_fcpu_probe(struct platform_dev= ice *pdev) struct tegra_dfll_soc_data *soc; const struct dfll_fcpu_data *fcpu_data; struct rail_alignment align; + u32 max_freq; =20 fcpu_data =3D of_device_get_match_data(&pdev->dev); if (!fcpu_data) @@ -589,7 +590,12 @@ static int tegra124_dfll_fcpu_probe(struct platform_de= vice *pdev) return err; } =20 - soc->max_freq =3D fcpu_data->cpu_max_freq_table[speedo_id]; + if (!of_property_read_u32(pdev->dev.of_node, + "nvidia,dfll-max-freq", + &max_freq)) + soc->max_freq =3D max_freq; + else + soc->max_freq =3D fcpu_data->cpu_max_freq_table[speedo_id]; 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Sat, 16 Aug 2025 05:54:19 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Sat, 16 Aug 2025 00:53:37 -0500 Subject: [PATCH 5/5] arm64: tegra: Limit max cpu frequency on P3450 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250816-tegra210-speedo-v1-5-a981360adc27@gmail.com> References: <20250816-tegra210-speedo-v1-0-a981360adc27@gmail.com> In-Reply-To: <20250816-tegra210-speedo-v1-0-a981360adc27@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Joseph Lo , Peter De Schrijver , Prashant Gaikwad Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Thierry Reding , Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755323658; l=935; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=JtR2frb8U61WYYSqhxHsZ+WqeNipPuKmeW1w+OFmzpU=; b=c8aF1tlFVKvuMAgjpH17Vx+W6YJ9ly6+2UZTmDmo879riiX6BemOb25Mah5RxcSAtHIDCI+VW kPtnx+v5hAcB7G6R9kog0SaaaP/PtAG4t6pc175XEY1HjM4RniK+1dA X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling P3450's cpu is only rated for 1.4 GHz while the CVB table it uses tries to scale to 1.5 GHz. Set an appropriate limit on the maximum scaling frequency. Signed-off-by: Aaron Kling --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm6= 4/boot/dts/nvidia/tegra210-p3450-0000.dts index ec0e84cb83ef9bf8f0e52e2958db33666813917c..10f878d3f50815d1f0297d15669= 048ab9cad73ee 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -594,6 +594,7 @@ clock@70110000 { nvidia,droop-ctrl =3D <0x00000f00>; nvidia,force-mode =3D <1>; nvidia,sample-rate =3D <25000>; + nvidia,dfll-max-freq =3D <1479000000>; =20 nvidia,pwm-min-microvolts =3D <708000>; nvidia,pwm-period-nanoseconds =3D <2500>; /* 2.5us */ --=20 2.50.1