The Glymur SoC TCSR block provides CLKREF clocks for EDP, PCIe, and USB. Add
this to the TCSR clock controller binding together with identifiers for
the clocks.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
.../bindings/clock/qcom,sm8550-tcsr.yaml | 3 +++
include/dt-bindings/clock/qcom,glymur-tcsr.h | 24 ++++++++++++++++++++++
2 files changed, 27 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
index 2ed7d59722fc7e1e8ccc3adbef16e26fc44bf156..2c992b3437f29b38d9c73e3c600f2c55e0b8ae98 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
@@ -8,12 +8,14 @@ title: Qualcomm TCSR Clock Controller on SM8550
maintainers:
- Bjorn Andersson <andersson@kernel.org>
+ - Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm TCSR clock control module provides the clocks, resets and
power domains on SM8550
See also:
+ - include/dt-bindings/clock/qcom,glymur-tcsr.h
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
- include/dt-bindings/clock/qcom,sm8650-tcsr.h
- include/dt-bindings/clock/qcom,sm8750-tcsr.h
@@ -22,6 +24,7 @@ properties:
compatible:
items:
- enum:
+ - qcom,glymur-tcsr
- qcom,milos-tcsr
- qcom,sar2130p-tcsr
- qcom,sm8550-tcsr
diff --git a/include/dt-bindings/clock/qcom,glymur-tcsr.h b/include/dt-bindings/clock/qcom,glymur-tcsr.h
new file mode 100644
index 0000000000000000000000000000000000000000..72614226b113bb60f1e430fc18e13c46c8b043d3
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,glymur-tcsr.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_GLYMUR_H
+#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_GLYMUR_H
+
+/* TCSR_CC clocks */
+#define TCSR_EDP_CLKREF_EN 0
+#define TCSR_PCIE_1_CLKREF_EN 1
+#define TCSR_PCIE_2_CLKREF_EN 2
+#define TCSR_PCIE_3_CLKREF_EN 3
+#define TCSR_PCIE_4_CLKREF_EN 4
+#define TCSR_USB2_1_CLKREF_EN 5
+#define TCSR_USB2_2_CLKREF_EN 6
+#define TCSR_USB2_3_CLKREF_EN 7
+#define TCSR_USB2_4_CLKREF_EN 8
+#define TCSR_USB3_0_CLKREF_EN 9
+#define TCSR_USB3_1_CLKREF_EN 10
+#define TCSR_USB4_1_CLKREF_EN 11
+#define TCSR_USB4_2_CLKREF_EN 12
+
+#endif
--
2.34.1
On Wed, Aug 13, 2025 at 01:25:18PM +0530, Taniya Das wrote: > The Glymur SoC TCSR block provides CLKREF clocks for EDP, PCIe, and USB. Add > this to the TCSR clock controller binding together with identifiers for > the clocks. If there is going to be resend: Please wrap commit message according to Linux coding style / submission process (neither too early nor over the limit): https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597 Best regards, Krzysztof
On 8/14/2025 1:37 PM, Krzysztof Kozlowski wrote: > On Wed, Aug 13, 2025 at 01:25:18PM +0530, Taniya Das wrote: >> The Glymur SoC TCSR block provides CLKREF clocks for EDP, PCIe, and USB. Add >> this to the TCSR clock controller binding together with identifiers for >> the clocks. > > If there is going to be resend: > > Please wrap commit message according to Linux coding style / submission > process (neither too early nor over the limit): > https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597 Sure will fix Krzysztof in the next patchset. -- Thanks, Taniya Das
On Wed, Aug 13, 2025 at 01:25:18PM +0530, Taniya Das wrote: > The Glymur SoC TCSR block provides CLKREF clocks for EDP, PCIe, and USB. Add > this to the TCSR clock controller binding together with identifiers for > the clocks. > > Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> > --- > .../bindings/clock/qcom,sm8550-tcsr.yaml | 3 +++ > include/dt-bindings/clock/qcom,glymur-tcsr.h | 24 ++++++++++++++++++++++ > 2 files changed, 27 insertions(+) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Wed, Aug 13, 2025 at 01:25:18PM +0530, Taniya Das wrote: > The Glymur SoC TCSR block provides CLKREF clocks for EDP, PCIe, and USB. Add > this to the TCSR clock controller binding together with identifiers for > the clocks. > Very nice, thank you! Reviewed-by: Bjorn Andersson <andersson@kernel.org> Regards, Bjorn > Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> > --- > .../bindings/clock/qcom,sm8550-tcsr.yaml | 3 +++ > include/dt-bindings/clock/qcom,glymur-tcsr.h | 24 ++++++++++++++++++++++ > 2 files changed, 27 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml > index 2ed7d59722fc7e1e8ccc3adbef16e26fc44bf156..2c992b3437f29b38d9c73e3c600f2c55e0b8ae98 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml > @@ -8,12 +8,14 @@ title: Qualcomm TCSR Clock Controller on SM8550 > > maintainers: > - Bjorn Andersson <andersson@kernel.org> > + - Taniya Das <taniya.das@oss.qualcomm.com> > > description: | > Qualcomm TCSR clock control module provides the clocks, resets and > power domains on SM8550 > > See also: > + - include/dt-bindings/clock/qcom,glymur-tcsr.h > - include/dt-bindings/clock/qcom,sm8550-tcsr.h > - include/dt-bindings/clock/qcom,sm8650-tcsr.h > - include/dt-bindings/clock/qcom,sm8750-tcsr.h > @@ -22,6 +24,7 @@ properties: > compatible: > items: > - enum: > + - qcom,glymur-tcsr > - qcom,milos-tcsr > - qcom,sar2130p-tcsr > - qcom,sm8550-tcsr > diff --git a/include/dt-bindings/clock/qcom,glymur-tcsr.h b/include/dt-bindings/clock/qcom,glymur-tcsr.h > new file mode 100644 > index 0000000000000000000000000000000000000000..72614226b113bb60f1e430fc18e13c46c8b043d3 > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,glymur-tcsr.h > @@ -0,0 +1,24 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_GLYMUR_H > +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_GLYMUR_H > + > +/* TCSR_CC clocks */ > +#define TCSR_EDP_CLKREF_EN 0 > +#define TCSR_PCIE_1_CLKREF_EN 1 > +#define TCSR_PCIE_2_CLKREF_EN 2 > +#define TCSR_PCIE_3_CLKREF_EN 3 > +#define TCSR_PCIE_4_CLKREF_EN 4 > +#define TCSR_USB2_1_CLKREF_EN 5 > +#define TCSR_USB2_2_CLKREF_EN 6 > +#define TCSR_USB2_3_CLKREF_EN 7 > +#define TCSR_USB2_4_CLKREF_EN 8 > +#define TCSR_USB3_0_CLKREF_EN 9 > +#define TCSR_USB3_1_CLKREF_EN 10 > +#define TCSR_USB4_1_CLKREF_EN 11 > +#define TCSR_USB4_2_CLKREF_EN 12 > + > +#endif > > -- > 2.34.1 >
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