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Wed, 13 Aug 2025 00:56:03 -0700 (PDT) X-Google-Smtp-Source: AGHT+IERFxv9gFWTq8pe8BgE9fFX8Kld5lCGhSgqJZoo2m38yCdBawTCYOPwqUMppj5BB8hBCFL8Dw== X-Received: by 2002:a05:6a00:2396:b0:76b:f1c0:224b with SMTP id d2e1a72fcca58-76e20fd02b7mr3433259b3a.23.1755071763502; Wed, 13 Aug 2025 00:56:03 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76bccfbd22csm31395754b3a.65.2025.08.13.00.55.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Aug 2025 00:56:03 -0700 (PDT) From: Taniya Das Date: Wed, 13 Aug 2025 13:25:18 +0530 Subject: [PATCH v4 2/7] dt-bindings: clock: qcom: Document the Glymur SoC TCSR Clock Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250813-glymur-clock-controller-v4-v4-2-a408b390b22c@oss.qualcomm.com> References: <20250813-glymur-clock-controller-v4-v4-0-a408b390b22c@oss.qualcomm.com> In-Reply-To: <20250813-glymur-clock-controller-v4-v4-0-a408b390b22c@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODExMDA3NCBTYWx0ZWRfX3aWHYNkP4fgf UNshZ+noGgvX6nRyHOfx9HcUsvaCpQLz4l5D+kVQi0IX2qeN5ab6lDnBytLPVvx+ppfg71tNzij uWCNHukGDE9qot5yiP5UBvAENqMaB6JtHf7/aWbOecqhg0SxeHzXleasrQ2Kjl91/rJQi+paAFE 8gMdLoExmR7cvgaNKz0xPf0m4MLzpU8FWd1/nDoFCi4PMv14g/WnWt6i+hzxfiMYKCPJk3wY5+6 Rhxn/LcueU2SaZBmbX6IZKHqWk9XiBTFY3nIkuDbfpMuf9nWTgGN1FeGGmGy69sLLzj2rqsYkrx KJo+aO3w24xcY96tpQUuf0nfVERzdmDDFBQoSI7OamoYR4+RremvgIaL+wBFhYsJ3Jm1fkueWHQ IWY7jYuS X-Proofpoint-GUID: 22D3EIlLzcpp9nQOnmL7oJvy8wqzyXO4 X-Authority-Analysis: v=2.4 cv=TJFFS0la c=1 sm=1 tr=0 ts=689c4515 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=NoBSHRPQAjGLFGKXj-wA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-ORIG-GUID: 22D3EIlLzcpp9nQOnmL7oJvy8wqzyXO4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_08,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 adultscore=0 impostorscore=0 malwarescore=0 phishscore=0 clxscore=1015 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508110074 The Glymur SoC TCSR block provides CLKREF clocks for EDP, PCIe, and USB. Add this to the TCSR clock controller binding together with identifiers for the clocks. Signed-off-by: Taniya Das Reviewed-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,sm8550-tcsr.yaml | 3 +++ include/dt-bindings/clock/qcom,glymur-tcsr.h | 24 ++++++++++++++++++= ++++ 2 files changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml = b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml index 2ed7d59722fc7e1e8ccc3adbef16e26fc44bf156..2c992b3437f29b38d9c73e3c600= f2c55e0b8ae98 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -8,12 +8,14 @@ title: Qualcomm TCSR Clock Controller on SM8550 =20 maintainers: - Bjorn Andersson + - Taniya Das =20 description: | Qualcomm TCSR clock control module provides the clocks, resets and power domains on SM8550 =20 See also: + - include/dt-bindings/clock/qcom,glymur-tcsr.h - include/dt-bindings/clock/qcom,sm8550-tcsr.h - include/dt-bindings/clock/qcom,sm8650-tcsr.h - include/dt-bindings/clock/qcom,sm8750-tcsr.h @@ -22,6 +24,7 @@ properties: compatible: items: - enum: + - qcom,glymur-tcsr - qcom,milos-tcsr - qcom,sar2130p-tcsr - qcom,sm8550-tcsr diff --git a/include/dt-bindings/clock/qcom,glymur-tcsr.h b/include/dt-bind= ings/clock/qcom,glymur-tcsr.h new file mode 100644 index 0000000000000000000000000000000000000000..72614226b113bb60f1e430fc18e= 13c46c8b043d3 --- /dev/null +++ b/include/dt-bindings/clock/qcom,glymur-tcsr.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_GLYMUR_H +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_GLYMUR_H + +/* TCSR_CC clocks */ +#define TCSR_EDP_CLKREF_EN 0 +#define TCSR_PCIE_1_CLKREF_EN 1 +#define TCSR_PCIE_2_CLKREF_EN 2 +#define TCSR_PCIE_3_CLKREF_EN 3 +#define TCSR_PCIE_4_CLKREF_EN 4 +#define TCSR_USB2_1_CLKREF_EN 5 +#define TCSR_USB2_2_CLKREF_EN 6 +#define TCSR_USB2_3_CLKREF_EN 7 +#define TCSR_USB2_4_CLKREF_EN 8 +#define TCSR_USB3_0_CLKREF_EN 9 +#define TCSR_USB3_1_CLKREF_EN 10 +#define TCSR_USB4_1_CLKREF_EN 11 +#define TCSR_USB4_2_CLKREF_EN 12 + +#endif --=20 2.34.1