Add Tesla FSD SoC support for both RC and EP.
Signed-off-by: Shradha Todi <shradha.t@samsung.com>
---
.../bindings/pci/tesla,fsd-pcie-ep.yaml | 91 +++++++++++++++++++
.../bindings/pci/tesla,fsd-pcie.yaml | 77 ++++++++++++++++
2 files changed, 168 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep.yaml
create mode 100644 Documentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep.yaml
new file mode 100644
index 000000000000..8dfe0720e6ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/tesla,fsd-pcie-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tesla FSD SoC series PCIe Endpoint Controller
+
+maintainers:
+ - Shradha Todi <shradha.t@samsung.com>
+
+description:
+ Tesla FSD SoCs PCIe endpoint controller is based on the Synopsys DesignWare
+ PCIe IP and thus inherits all the common properties defined in
+ snps,dw-pcie-ep.yaml
+
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
+
+properties:
+ compatible:
+ const: tesla,fsd-pcie-ep
+
+ reg:
+ maxItems: 4
+
+ reg-names:
+ items:
+ - const: elbi
+ - const: dbi
+ - const: dbi2
+ - const: addr_space
+
+ clocks:
+ maxItems: 4
+
+ clock-names:
+ items:
+ - const: aux
+ - const: dbi
+ - const: mstr
+ - const: slv
+
+ num-lanes:
+ maximum: 4
+
+ phys:
+ maxItems: 1
+
+ samsung,syscon-pcie:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: phandle for system control registers, used to
+ control signals at system level
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - num-lanes
+ - phys
+ - samsung,syscon-pcie
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/fsd-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ pcieep0: pcie-ep@16a00000 {
+ compatible = "tesla,fsd-pcie-ep";
+ reg = <0x0 0x168b0000 0x0 0x1000>,
+ <0x0 0x16a00000 0x0 0x2000>,
+ <0x0 0x16a01000 0x0 0x80>,
+ <0x0 0x17000000 0x0 0xff0000>;
+ reg-names = "elbi", "dbi", "dbi2", "addr_space";
+ clocks = <&clock_fsys1 PCIE_LINK0_IPCLKPORT_AUX_ACLK>,
+ <&clock_fsys1 PCIE_LINK0_IPCLKPORT_DBI_ACLK>,
+ <&clock_fsys1 PCIE_LINK0_IPCLKPORT_MSTR_ACLK>,
+ <&clock_fsys1 PCIE_LINK0_IPCLKPORT_SLV_ACLK>;
+ clock-names = "aux", "dbi", "mstr", "slv";
+ num-lanes = <4>;
+ phys = <&pciephy1>;
+ samsung,syscon-pcie = <&sysreg_fsys1 0x50c>;
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml b/Documentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml
new file mode 100644
index 000000000000..533870ab1d73
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/tesla,fsd-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tesla FSD SoC series PCIe Host Controller
+
+maintainers:
+ - Shradha Todi <shradha.t@samsung.com>
+
+description:
+ Tesla FSD SoCs PCIe host controller inherits all the common
+ properties defined in samsung,exynos-pcie.yaml
+
+allOf:
+ - $ref: /schemas/pci/samsung,exynos-pcie.yaml#
+
+properties:
+ compatible:
+ const: tesla,fsd-pcie
+
+ clocks:
+ maxItems: 4
+
+ clock-names:
+ items:
+ - const: aux
+ - const: dbi
+ - const: mstr
+ - const: slv
+
+ num-lanes:
+ maximum: 4
+
+ samsung,syscon-pcie:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: phandle for system control registers, used to
+ control signals at system level
+
+required:
+ - samsung,syscon-pcie
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/fsd-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcierc1: pcie@16b00000 {
+ compatible = "tesla,fsd-pcie";
+ reg = <0x0 0x16b00000 0x0 0x2000>,
+ <0x0 0x168c0000 0x0 0x1000>,
+ <0x0 0x18000000 0x0 0x1000>;
+ reg-names = "dbi", "elbi", "config";
+ ranges = <0x82000000 0x0 0x18001000 0x0 0x18001000 0x0 0xffefff>;
+ clocks = <&clock_fsys1 PCIE_LINK1_IPCLKPORT_AUX_ACLK>,
+ <&clock_fsys1 PCIE_LINK1_IPCLKPORT_DBI_ACLK>,
+ <&clock_fsys1 PCIE_LINK1_IPCLKPORT_MSTR_ACLK>,
+ <&clock_fsys1 PCIE_LINK1_IPCLKPORT_SLV_ACLK>;
+ clock-names = "aux", "dbi", "mstr", "slv";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ dma-coherent;
+ device_type = "pci";
+ interrupts = <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>;
+ num-lanes = <4>;
+ phys = <&pciephy1>;
+ samsung,syscon-pcie = <&sysreg_fsys1 0x510>;
+ };
+ };
+...
--
2.49.0On Mon, Aug 11, 2025 at 09:16:33PM GMT, Shradha Todi wrote:
> Add Tesla FSD SoC support for both RC and EP.
Add some info about the PCIe controller here. Like the data rate supported,
lanes, interrupts, any quirks etc...
>
> Signed-off-by: Shradha Todi <shradha.t@samsung.com>
> ---
> .../bindings/pci/tesla,fsd-pcie-ep.yaml | 91 +++++++++++++++++++
> .../bindings/pci/tesla,fsd-pcie.yaml | 77 ++++++++++++++++
> 2 files changed, 168 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep.yaml
> create mode 100644 Documentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml
>
[...]
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/fsd-clk.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + pcierc1: pcie@16b00000 {
> + compatible = "tesla,fsd-pcie";
> + reg = <0x0 0x16b00000 0x0 0x2000>,
> + <0x0 0x168c0000 0x0 0x1000>,
> + <0x0 0x18000000 0x0 0x1000>;
> + reg-names = "dbi", "elbi", "config";
> + ranges = <0x82000000 0x0 0x18001000 0x0 0x18001000 0x0 0xffefff>;
> + clocks = <&clock_fsys1 PCIE_LINK1_IPCLKPORT_AUX_ACLK>,
> + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_DBI_ACLK>,
> + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_MSTR_ACLK>,
> + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_SLV_ACLK>;
> + clock-names = "aux", "dbi", "mstr", "slv";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + dma-coherent;
> + device_type = "pci";
> + interrupts = <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>;
Only one SPI interrupt? What about INTx? Don't you have any external/internal
MSI controller?
- Mani
--
மணிவண்ணன் சதாசிவம்
On 11/08/2025 17:46, Shradha Todi wrote:
> +
> + clocks:
> + maxItems: 4
> +
> + clock-names:
> + items:
> + - const: aux
> + - const: dbi
> + - const: mstr
> + - const: slv
> +
> + num-lanes:
> + maximum: 4
> +
> + phys:
> + maxItems: 1
> +
> + samsung,syscon-pcie:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: phandle for system control registers, used to
> + control signals at system level
What is "system level"? and what are these "signals" being controlled?
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - num-lanes
> + - phys
> + - samsung,syscon-pcie
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/fsd-clk.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + bus {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + pcieep0: pcie-ep@16a00000 {
> + compatible = "tesla,fsd-pcie-ep";
> + reg = <0x0 0x168b0000 0x0 0x1000>,
> + <0x0 0x16a00000 0x0 0x2000>,
> + <0x0 0x16a01000 0x0 0x80>,
> + <0x0 0x17000000 0x0 0xff0000>;
> + reg-names = "elbi", "dbi", "dbi2", "addr_space";
> + clocks = <&clock_fsys1 PCIE_LINK0_IPCLKPORT_AUX_ACLK>,
> + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_DBI_ACLK>,
> + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_MSTR_ACLK>,
> + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_SLV_ACLK>;
> + clock-names = "aux", "dbi", "mstr", "slv";
> + num-lanes = <4>;
> + phys = <&pciephy1>;
> + samsung,syscon-pcie = <&sysreg_fsys1 0x50c>;
> + };
> + };
> +...
> diff --git a/Documentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml b/Documentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml
> new file mode 100644
> index 000000000000..533870ab1d73
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml
> @@ -0,0 +1,77 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/tesla,fsd-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Tesla FSD SoC series PCIe Host Controller
> +
> +maintainers:
> + - Shradha Todi <shradha.t@samsung.com>
> +
> +description:
> + Tesla FSD SoCs PCIe host controller inherits all the common
> + properties defined in samsung,exynos-pcie.yaml
> +
> +allOf:
> + - $ref: /schemas/pci/samsung,exynos-pcie.yaml#
> +
> +properties:
> + compatible:
> + const: tesla,fsd-pcie
> +
> + clocks:
> + maxItems: 4
> +
> + clock-names:
> + items:
> + - const: aux
> + - const: dbi
> + - const: mstr
> + - const: slv
> +
> + num-lanes:
> + maximum: 4
> +
> + samsung,syscon-pcie:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: phandle for system control registers, used to
> + control signals at system level
> +
> +required:
> + - samsung,syscon-pcie
clocks are required, compatible as well.
Missing supplies, both as properties and required. PCI devices do not
work without power.
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/fsd-clk.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + pcierc1: pcie@16b00000 {
> + compatible = "tesla,fsd-pcie";
> + reg = <0x0 0x16b00000 0x0 0x2000>,
> + <0x0 0x168c0000 0x0 0x1000>,
> + <0x0 0x18000000 0x0 0x1000>;
> + reg-names = "dbi", "elbi", "config";
> + ranges = <0x82000000 0x0 0x18001000 0x0 0x18001000 0x0 0xffefff>;
Misaligned. Follow closely DTS coding style.
> + clocks = <&clock_fsys1 PCIE_LINK1_IPCLKPORT_AUX_ACLK>,
> + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_DBI_ACLK>,
> + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_MSTR_ACLK>,
> + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_SLV_ACLK>;
> + clock-names = "aux", "dbi", "mstr", "slv";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + dma-coherent;
> + device_type = "pci";
> + interrupts = <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>;
> + num-lanes = <4>;
> + phys = <&pciephy1>;
> + samsung,syscon-pcie = <&sysreg_fsys1 0x510>;
Incomplete, missing supplies.
> + };
> + };
> +...
Best regards,
Krzysztof
> > +
> > + phys:
> > + maxItems: 1
> > +
> > + samsung,syscon-pcie:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description: phandle for system control registers, used to
> > + control signals at system level
>
> What is "system level"? and what are these "signals" being controlled?
>
I will add a more detailed description for why the syscon is being used
>
> > +title: Tesla FSD SoC series PCIe Host Controller
> > +
> > +maintainers:
> > + - Shradha Todi <shradha.t@samsung.com>
> > +
> > +description:
> > + Tesla FSD SoCs PCIe host controller inherits all the common
> > + properties defined in samsung,exynos-pcie.yaml
> > +
> > +allOf:
> > + - $ref: /schemas/pci/samsung,exynos-pcie.yaml#
> > +
> > +properties:
> > + compatible:
> > + const: tesla,fsd-pcie
> > +
> > + clocks:
> > + maxItems: 4
> > +
> > + clock-names:
> > + items:
> > + - const: aux
> > + - const: dbi
> > + - const: mstr
> > + - const: slv
> > +
> > + num-lanes:
> > + maximum: 4
> > +
> > + samsung,syscon-pcie:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description: phandle for system control registers, used to
> > + control signals at system level
> > +
> > +required:
> > + - samsung,syscon-pcie
>
> clocks are required, compatible as well.
>
Since this was inheriting the common exynos yaml file and that had these properties
under required, I did not mention again. Will take care in next version.
> Missing supplies, both as properties and required. PCI devices do not
> work without power.
>
According to the HW design of FSD SoC, the control to manage PCIe power is given to
a separate CPU where custom firmware runs. Therefore, the Linux side does not control
the PCIe power supplies directly and are hence not included in the device tree.
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/fsd-clk.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + pcierc1: pcie@16b00000 {
> > + compatible = "tesla,fsd-pcie";
> > + reg = <0x0 0x16b00000 0x0 0x2000>,
> > + <0x0 0x168c0000 0x0 0x1000>,
> > + <0x0 0x18000000 0x0 0x1000>;
> > + reg-names = "dbi", "elbi", "config";
> > + ranges = <0x82000000 0x0 0x18001000 0x0 0x18001000 0x0 0xffefff>;
>
> Misaligned. Follow closely DTS coding style.
>
Will take care.
On Mon, Aug 18, 2025 at 02:16:16PM GMT, Shradha Todi wrote: > > > + > > > + phys: > > > + maxItems: 1 > > > + > > > + samsung,syscon-pcie: > > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > > + description: phandle for system control registers, used to > > > + control signals at system level > > > > What is "system level"? and what are these "signals" being controlled? > > > > I will add a more detailed description for why the syscon is being used > > > > > > +title: Tesla FSD SoC series PCIe Host Controller > > > + > > > +maintainers: > > > + - Shradha Todi <shradha.t@samsung.com> > > > + > > > +description: > > > + Tesla FSD SoCs PCIe host controller inherits all the common > > > + properties defined in samsung,exynos-pcie.yaml > > > + > > > +allOf: > > > + - $ref: /schemas/pci/samsung,exynos-pcie.yaml# > > > + > > > +properties: > > > + compatible: > > > + const: tesla,fsd-pcie > > > + > > > + clocks: > > > + maxItems: 4 > > > + > > > + clock-names: > > > + items: > > > + - const: aux > > > + - const: dbi > > > + - const: mstr > > > + - const: slv > > > + > > > + num-lanes: > > > + maximum: 4 > > > + > > > + samsung,syscon-pcie: > > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > > + description: phandle for system control registers, used to > > > + control signals at system level > > > + > > > +required: > > > + - samsung,syscon-pcie > > > > clocks are required, compatible as well. > > > > Since this was inheriting the common exynos yaml file and that had these properties > under required, I did not mention again. Will take care in next version. > dma-coherent needs to be a required property as well since this binding is supporting only one controller, that seem to have cache coherent DMA. > > Missing supplies, both as properties and required. PCI devices do not > > work without power. > > > > According to the HW design of FSD SoC, the control to manage PCIe power is given to > a separate CPU where custom firmware runs. Therefore, the Linux side does not control > the PCIe power supplies directly and are hence not included in the device tree. What do you mean by 'PCIe power'? Supply to the PCIe controller/bus or the devices connected to the bus? - Mani -- மணிவண்ணன் சதாசிவம்
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