From nobody Sun Oct 5 02:11:27 2025 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90A262DFA2A for ; Tue, 12 Aug 2025 05:02:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.24 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754974948; cv=none; b=AWTmjZldZIRTGNvxpd780VhROK+J85bIIZ/4qSbcmlpMKaYFCZabhj35hf5CH835s0paumP2+Y7WEyZmXn/JwrcHGZQc+LQcwWwWk96r2RRHHOWWPWWA42sVwajTm5qJCbBOzLhZ/dszrIKV4XLSLJWZ0g9mWk8oP1Biy+Prua4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754974948; c=relaxed/simple; bh=tv5C5NrFgbEK0Qz216ihnRUh0xGyrEHHx6MTG0wFdsA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:MIME-Version: Content-Type:References; b=txvM5kgAxsr5JyGEtHwDGsEthOmJ4D9PzsD/DlZz2iKVlZRnxawaxRbrJaFQzAKB07rA34hUocILfE4jKFLyshaTlfmHi0ihbZB7IYOR494HvdRSuMMWl/ZtGqFM7g+W5UhD9vlIm7lBr10lbnOkhVqvUIJohXCUh2jKsEm1h2o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=JeTPDnYu; arc=none smtp.client-ip=203.254.224.24 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="JeTPDnYu" Received: from epcas5p4.samsung.com (unknown [182.195.41.42]) by mailout1.samsung.com (KnoxPortal) with ESMTP id 20250812050225epoutp0144d60477bc410c6cfc9cd6664d442650~a7GoODEX81032210322epoutp01_ for ; Tue, 12 Aug 2025 05:02:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.samsung.com 20250812050225epoutp0144d60477bc410c6cfc9cd6664d442650~a7GoODEX81032210322epoutp01_ DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1754974945; bh=S54LpcLjSITXFL38Nc1C+zVT40bjsTQzlIyqclkPzVo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JeTPDnYuQFKjUOTf8Qf/JgacAWkUrVaPAAmH0gatq5vLSDCszPks4Do5/rniN7fB9 yZBekS8tCKsz8fV8oRIwvUOdA1wrRX3vrHkKhZyZ64XDj35FqGHw15Zu453CsrZriX 0LPAoRJHEgU+4LKVWr0O92l/CL0yN3YU1dgHYoB4= Received: from epsnrtp02.localdomain (unknown [182.195.42.154]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPS id 20250812050224epcas5p4e05b55a5f45f116cf966dc700093eba8~a7GnpBriA0263302633epcas5p4v; Tue, 12 Aug 2025 05:02:24 +0000 (GMT) Received: from epcas5p4.samsung.com (unknown [182.195.38.95]) by epsnrtp02.localdomain (Postfix) with ESMTP id 4c1KB72z6Rz2SSKp; Tue, 12 Aug 2025 05:02:23 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPA id 20250811154725epcas5p428fa3370a32bc2b664a4fd8260078097~awQg8dEdu2612226122epcas5p4y; Mon, 11 Aug 2025 15:47:25 +0000 (GMT) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250811154723epsmtip1209187009cea317303c81d1a099486b6~awQeURXHq2560925609epsmtip1Q; Mon, 11 Aug 2025 15:47:22 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, pankaj.dubey@samsung.com, Shradha Todi Subject: [PATCH v3 07/12] dt-bindings: PCI: Add support for Tesla FSD SoC Date: Mon, 11 Aug 2025 21:16:33 +0530 Message-ID: <20250811154638.95732-8-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250811154638.95732-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250811154725epcas5p428fa3370a32bc2b664a4fd8260078097 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250811154725epcas5p428fa3370a32bc2b664a4fd8260078097 References: <20250811154638.95732-1-shradha.t@samsung.com> Add Tesla FSD SoC support for both RC and EP. Signed-off-by: Shradha Todi --- .../bindings/pci/tesla,fsd-pcie-ep.yaml | 91 +++++++++++++++++++ .../bindings/pci/tesla,fsd-pcie.yaml | 77 ++++++++++++++++ 2 files changed, 168 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep= .yaml create mode 100644 Documentation/devicetree/bindings/pci/tesla,fsd-pcie.ya= ml diff --git a/Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep.yaml b= /Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep.yaml new file mode 100644 index 000000000000..8dfe0720e6ab --- /dev/null +++ b/Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/tesla,fsd-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tesla FSD SoC series PCIe Endpoint Controller + +maintainers: + - Shradha Todi + +description: + Tesla FSD SoCs PCIe endpoint controller is based on the Synopsys DesignW= are + PCIe IP and thus inherits all the common properties defined in + snps,dw-pcie-ep.yaml + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + +properties: + compatible: + const: tesla,fsd-pcie-ep + + reg: + maxItems: 4 + + reg-names: + items: + - const: elbi + - const: dbi + - const: dbi2 + - const: addr_space + + clocks: + maxItems: 4 + + clock-names: + items: + - const: aux + - const: dbi + - const: mstr + - const: slv + + num-lanes: + maximum: 4 + + phys: + maxItems: 1 + + samsung,syscon-pcie: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: phandle for system control registers, used to + control signals at system level + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - num-lanes + - phys + - samsung,syscon-pcie + +unevaluatedProperties: false + +examples: + - | + #include + #include + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + pcieep0: pcie-ep@16a00000 { + compatible =3D "tesla,fsd-pcie-ep"; + reg =3D <0x0 0x168b0000 0x0 0x1000>, + <0x0 0x16a00000 0x0 0x2000>, + <0x0 0x16a01000 0x0 0x80>, + <0x0 0x17000000 0x0 0xff0000>; + reg-names =3D "elbi", "dbi", "dbi2", "addr_space"; + clocks =3D <&clock_fsys1 PCIE_LINK0_IPCLKPORT_AUX_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_DBI_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_MSTR_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_SLV_ACLK>; + clock-names =3D "aux", "dbi", "mstr", "slv"; + num-lanes =3D <4>; + phys =3D <&pciephy1>; + samsung,syscon-pcie =3D <&sysreg_fsys1 0x50c>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml b/Do= cumentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml new file mode 100644 index 000000000000..533870ab1d73 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/tesla,fsd-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tesla FSD SoC series PCIe Host Controller + +maintainers: + - Shradha Todi + +description: + Tesla FSD SoCs PCIe host controller inherits all the common + properties defined in samsung,exynos-pcie.yaml + +allOf: + - $ref: /schemas/pci/samsung,exynos-pcie.yaml# + +properties: + compatible: + const: tesla,fsd-pcie + + clocks: + maxItems: 4 + + clock-names: + items: + - const: aux + - const: dbi + - const: mstr + - const: slv + + num-lanes: + maximum: 4 + + samsung,syscon-pcie: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: phandle for system control registers, used to + control signals at system level + +required: + - samsung,syscon-pcie + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcierc1: pcie@16b00000 { + compatible =3D "tesla,fsd-pcie"; + reg =3D <0x0 0x16b00000 0x0 0x2000>, + <0x0 0x168c0000 0x0 0x1000>, + <0x0 0x18000000 0x0 0x1000>; + reg-names =3D "dbi", "elbi", "config"; + ranges =3D <0x82000000 0x0 0x18001000 0x0 0x18001000 0x0 0xff= efff>; + clocks =3D <&clock_fsys1 PCIE_LINK1_IPCLKPORT_AUX_ACLK>, + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_DBI_ACLK>, + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_MSTR_ACLK>, + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_SLV_ACLK>; + clock-names =3D "aux", "dbi", "mstr", "slv"; + #address-cells =3D <3>; + #size-cells =3D <2>; + dma-coherent; + device_type =3D "pci"; + interrupts =3D ; + num-lanes =3D <4>; + phys =3D <&pciephy1>; + samsung,syscon-pcie =3D <&sysreg_fsys1 0x510>; + }; + }; +... --=20 2.49.0