This one is applied for loongarch-fixes.
Huacai
On Mon, Aug 11, 2025 at 10:15 AM Bibo Mao <maobibo@loongson.cn> wrote:
>
> With pch_pic device, its register is based on MMIO address space,
> different access size 1/2/4/8 is supported. And base address should
> be naturally aligned with its access size, here add alignment check
> in its register access emulation function.
>
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
> arch/loongarch/kvm/intc/pch_pic.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/loongarch/kvm/intc/pch_pic.c b/arch/loongarch/kvm/intc/pch_pic.c
> index 0710b5ab286e..5ee24dbf3c4c 100644
> --- a/arch/loongarch/kvm/intc/pch_pic.c
> +++ b/arch/loongarch/kvm/intc/pch_pic.c
> @@ -151,6 +151,11 @@ static int kvm_pch_pic_read(struct kvm_vcpu *vcpu,
> return -EINVAL;
> }
>
> + if (addr & (len - 1)) {
> + kvm_err("%s: pch pic not aligned addr %llx len %d\n", __func__, addr, len);
> + return -EINVAL;
> + }
> +
> /* statistics of pch pic reading */
> vcpu->stat.pch_pic_read_exits++;
> ret = loongarch_pch_pic_read(s, addr, len, val);
> @@ -246,6 +251,11 @@ static int kvm_pch_pic_write(struct kvm_vcpu *vcpu,
> return -EINVAL;
> }
>
> + if (addr & (len - 1)) {
> + kvm_err("%s: pch pic not aligned addr %llx len %d\n", __func__, addr, len);
> + return -EINVAL;
> + }
> +
> /* statistics of pch pic writing */
> vcpu->stat.pch_pic_write_exits++;
> ret = loongarch_pch_pic_write(s, addr, len, val);
> --
> 2.39.3
>
>