arch/arm64/boot/dts/qcom/sc7280.dtsi | 134 +++++++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+)
Only one PCIe controller has been described so far, but the SC7280 has
two controllers/phys. Describe the second one as well.
Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 134 +++++++++++++++++++++++++++++++++++
1 file changed, 134 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 64a2abd3010018e94eb50c534a509d6b4cf2473b..e44678b27226b8a911d8d2afa39092aa33396bec 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2200,6 +2200,135 @@ wifi: wifi@17a10040 {
qcom,smem-state-names = "wlan-smp2p-out";
};
+ pcie0: pcie@1c00000 {
+ compatible = "qcom,pcie-sc7280";
+ reg = <0 0x01c00000 0 0x3000>,
+ <0 0x60000000 0 0xf1d>,
+ <0 0x60000f20 0 0xa8>,
+ <0 0x60001000 0 0x1000>,
+ <0 0x60100000 0 0x100000>,
+ <0 0x01c03000 0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
+ <&pcie0_phy>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
+ clock-names = "pipe",
+ "pipe_mux",
+ "phy_pipe",
+ "ref",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "tbu",
+ "ddrss_sf_tbu",
+ "aggre0",
+ "aggre1";
+
+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+ <0x100 &apps_smmu 0x1c01 0x1>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc GCC_PCIE_0_GDSC>;
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_clkreq_n>;
+ dma-coherent;
+
+ status = "disabled";
+
+ pcie0_port: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+
+ pcie0_phy: phy@1c06000 {
+ compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
+ reg = <0 0x01c06000 0 0x1000>;
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_CLKREF_EN>,
+ <&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "refgen",
+ "pipe";
+
+ clock-output-names = "pcie_0_pipe_clk";
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
+
+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+ reset-names = "phy";
+
+ assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ status = "disabled";
+ };
+
pcie1: pcie@1c08000 {
compatible = "qcom,pcie-sc7280";
reg = <0 0x01c08000 0 0x3000>,
@@ -5285,6 +5414,11 @@ mi2s1_ws: mi2s1-ws-state {
function = "mi2s1_ws";
};
+ pcie0_clkreq_n: pcie0-clkreq-n-state {
+ pins = "gpio88";
+ function = "pcie0_clkreqn";
+ };
+
pcie1_clkreq_n: pcie1-clkreq-n-state {
pins = "gpio79";
function = "pcie1_clkreqn";
---
base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585
change-id: 20250811-sc7280-pcie0-163237b51baf
Best regards,
--
Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
On Mon, 11 Aug 2025 22:16:29 -0500, Bjorn Andersson wrote:
> Only one PCIe controller has been described so far, but the SC7280 has
> two controllers/phys. Describe the second one as well.
>
>
Applied, thanks!
[1/1] arm64: dts: qcom: sc7280: Describe the first PCIe controller and PHY
commit: f8328b7549e1faff45e32ab2ecc2573b90604e76
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
On 8/12/25 5:16 AM, Bjorn Andersson wrote:
> Only one PCIe controller has been described so far, but the SC7280 has
> two controllers/phys. Describe the second one as well.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> ---
[...]
> + pcie0_phy: phy@1c06000 {
> + compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
:(
BTW I noticed that Krishna also tackled the same issue just yesterday
on the internal mailing list.. would you prefer him to take it, or do
you want me to review this patch instead?
Konrad
On Tue, Aug 12, 2025 at 01:34:44PM +0200, Konrad Dybcio wrote:
> On 8/12/25 5:16 AM, Bjorn Andersson wrote:
> > Only one PCIe controller has been described so far, but the SC7280 has
> > two controllers/phys. Describe the second one as well.
> >
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> > ---
>
> [...]
>
> > + pcie0_phy: phy@1c06000 {
> > + compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
>
> :(
>
> BTW I noticed that Krishna also tackled the same issue just yesterday
> on the internal mailing list.. would you prefer him to take it, or do
> you want me to review this patch instead?
That means one thing: a lot of our engineers don't need to post patches
to the internal ML.
--
With best wishes
Dmitry
On 12/08/2025 16:45, Dmitry Baryshkov wrote:
> On Tue, Aug 12, 2025 at 01:34:44PM +0200, Konrad Dybcio wrote:
>> On 8/12/25 5:16 AM, Bjorn Andersson wrote:
>>> Only one PCIe controller has been described so far, but the SC7280 has
>>> two controllers/phys. Describe the second one as well.
>>>
>>> Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
>>> ---
>>
>> [...]
>>
>>> + pcie0_phy: phy@1c06000 {
>>> + compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
>>
>> :(
>>
>> BTW I noticed that Krishna also tackled the same issue just yesterday
>> on the internal mailing list.. would you prefer him to take it, or do
>> you want me to review this patch instead?
>
> That means one thing: a lot of our engineers don't need to post patches
> to the internal ML.
Or waiting between v1 and v2 could be shortened to less than 2 years.
Best regards,
Krzysztof
On 12/08/2025 05:16, Bjorn Andersson wrote: > Only one PCIe controller has been described so far, but the SC7280 has > two controllers/phys. Describe the second one as well. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 134 +++++++++++++++++++++++++++++++++++ > 1 file changed, 134 insertions(+) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Mon, Aug 11, 2025 at 10:16:29PM -0500, Bjorn Andersson wrote: > Only one PCIe controller has been described so far, but the SC7280 has > two controllers/phys. Describe the second one as well. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 134 +++++++++++++++++++++++++++++++++++ > 1 file changed, 134 insertions(+) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> -- With best wishes Dmitry
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