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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-61b7c8905e1sm1251129eaf.9.2025.08.11.20.16.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 20:16:35 -0700 (PDT) From: Bjorn Andersson Date: Mon, 11 Aug 2025 22:16:29 -0500 Subject: [PATCH] arm64: dts: qcom: sc7280: Describe the first PCIe controller and PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-sc7280-pcie0-v1-1-6093e5b208f9@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAAyymmgC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDI1MDC0ND3eJkcyMLA92C5MxUA11DM2MjY/MkU8OkxDQloJaCotS0zAqwcdG xtbUAC4GePl4AAAA= X-Change-ID: 20250811-sc7280-pcie0-163237b51baf To: cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Andersson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4939; i=bjorn.andersson@oss.qualcomm.com; h=from:subject:message-id; bh=skyJQGwtjusd2fTyqK4jZTr1TkF8k+4YfPyQ2SN6Icg=; b=owEBgwJ8/ZANAwAIAQsfOT8Nma3FAcsmYgBomrISIZSeuj4FYKAuRReAwOUK3oe0oyISoHypu A76YnT8bcyJAkkEAAEIADMWIQQF3gPMXzXqTwlm1SULHzk/DZmtxQUCaJqyEhUcYW5kZXJzc29u QGtlcm5lbC5vcmcACgkQCx85Pw2ZrcXGjhAAgnvRW0Kfci0GhBs/HKWfGL9HrK9Sa1BXInP3qi/ dNbJfSzGQxtTAYz7UCPa7QMpIh9UhaVVRLC/QXTJz0TOvHCRbObnQmhcFi++uefNBAfA2OyryDw /e8U+X8+u3wc+98fcDzkxiDit+Ew7cRj/AbTI8AqoD+dxHWTrpY6mweMzoCtcS1W0jw7lEhvU6Y IDBc41MOLsL0XpMCWfHm3sAAoP1gmQ508Ns4Qy8TR2FbOTPnBnPyylPTSUwr0iBSNSDbLezKqkF 9AG2/b3jnDvM2gyQJA9cUS9ySGNDJrJBczzTrN2Mxkp/MNC4bFP6+C8sLbIq8trXMHjWP06Yecr KEwgwzcPEZJ74QEsIhxd1UylRpl8xTrJNnNfO7xDRtci2A18UHVBr1Qe+KIAZX9Puqv378Op7P7 K82XLGjp4A9iCpC5wKSOZwkFO3YGuPsdrUFornQfD4rMbfgJJ2dqS/6DJHDrNyj7ozRVz9DEKA0 Jpfa0G5jTgGbSg14XCWRZHpqNTDy2ayIBzj5vmzIw3jyHpt+I+Kyn8DHYt/+eteaWg5AFPAD7f5 zthottp3mug0XunYZv1TLxkjjyJ8p1EATNxdqrAqXdW75lCGO9JtyQqOj1eBSjrL1wshWWCjLOu GJhWSffjVjdxQODhZv91+VUBT4KLLkLFpDQOy6ZL3D1M= X-Developer-Key: i=bjorn.andersson@oss.qualcomm.com; a=openpgp; fpr=05DE03CC5F35EA4F0966D5250B1F393F0D99ADC5 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODExMDA3NSBTYWx0ZWRfXwHbP+DFhu+du rEkyQfkPr8rEH/BOwKJtf3dZs2Yki4ZJCOh+i3fPzbbKYcgAfl60A7sg+wZr+cR2pFdo0QHfZso fxojjPC4lOTwPJAQvmfpc4lconP3Kn20ohEXOuTqgL5pcyWNbg1+5HV843P7qJPjRODpis2z8/x e5yGNtiZKOJa2P38WzlzliH5HuzTvdsG/J2v/2CGU3Yr8yneG+zyCPqtNML/EI+X+JLOI5nFkuW ggvhm1GUZZ17j+UK1bqTfyiiooUkhkZXwmVFPOzkX86SK/9GTXbi1CwJ38t2DqH98UbL7zgLJHQ 5kyyZ8YwmJ+qaWcThImBu8cYU425rrgca/RdUVWv8ztXXvjwvfzbo+6K2aRzAo6PxGip+S4t3bW MFSWUoEp X-Authority-Analysis: v=2.4 cv=TLZFS0la c=1 sm=1 tr=0 ts=689ab215 cx=c_pps a=7uPEO8VhqeOX8vTJ3z8K6Q==:117 a=DaeiM5VmU20ml6RIjrOvYw==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=SrWXOAHHq75Mue0GltgA:9 a=QEXdDO2ut3YA:10 a=EXS-LbY8YePsIyqnH6vw:22 X-Proofpoint-GUID: EXwrCpqfB1fLlNnytfpJoOCVdqUxLUdo X-Proofpoint-ORIG-GUID: EXwrCpqfB1fLlNnytfpJoOCVdqUxLUdo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_01,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 malwarescore=0 spamscore=0 priorityscore=1501 bulkscore=0 adultscore=0 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508110075 Only one PCIe controller has been described so far, but the SC7280 has two controllers/phys. Describe the second one as well. Signed-off-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 134 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 134 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 64a2abd3010018e94eb50c534a509d6b4cf2473b..e44678b27226b8a911d8d2afa39= 092aa33396bec 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2200,6 +2200,135 @@ wifi: wifi@17a10040 { qcom,smem-state-names =3D "wlan-smp2p-out"; }; =20 + pcie0: pcie@1c00000 { + compatible =3D "qcom,pcie-sc7280"; + reg =3D <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>, + <0 0x01c03000 0 0x1000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config", "mhi"; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + bus-range =3D <0x00 0xff>; + num-lanes =3D <1>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&pcie0_phy>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; + clock-names =3D "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu", + "aggre0", + "aggre1"; + + iommu-map =3D <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + resets =3D <&gcc GCC_PCIE_0_BCR>; + reset-names =3D "pci"; + + power-domains =3D <&gcc GCC_PCIE_0_GDSC>; + + phys =3D <&pcie0_phy>; + phy-names =3D "pciephy"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie0_clkreq_n>; + dma-coherent; + + status =3D "disabled"; + + pcie0_port: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie0_phy: phy@1c06000 { + compatible =3D "qcom,sm8250-qmp-gen3x1-pcie-phy"; + reg =3D <0 0x01c06000 0 0x1000>; + + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + + clock-output-names =3D "pcie_0_pipe_clk"; + #clock-cells =3D <0>; + + #phy-cells =3D <0>; + + resets =3D <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names =3D "phy"; + + assigned-clocks =3D <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + status =3D "disabled"; + }; + pcie1: pcie@1c08000 { compatible =3D "qcom,pcie-sc7280"; reg =3D <0 0x01c08000 0 0x3000>, @@ -5285,6 +5414,11 @@ mi2s1_ws: mi2s1-ws-state { function =3D "mi2s1_ws"; }; =20 + pcie0_clkreq_n: pcie0-clkreq-n-state { + pins =3D "gpio88"; + function =3D "pcie0_clkreqn"; + }; + pcie1_clkreq_n: pcie1-clkreq-n-state { pins =3D "gpio79"; function =3D "pcie1_clkreqn"; --- base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585 change-id: 20250811-sc7280-pcie0-163237b51baf Best regards, --=20 Bjorn Andersson