Add Iris video codec to SM8750 SoC, which comes with significantly
different powering up sequence than previous SM8650, thus different
clocks and resets. For consistency keep existing clock and clock-names
naming, so the list shares common part.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
qcom,sm8750-videocc bindings and clock headers dependency (will fail
build):
https://lore.kernel.org/all/20241206-sm8750_videocc-v1-0-5da6e7eea2bd@quicinc.com/
qcom,sm8750-iris bindings:
https://lore.kernel.org/r/20250804-sm8750-iris-v2-0-6d78407f8078@linaro.org
---
arch/arm64/boot/dts/qcom/sm8750.dtsi | 113 +++++++++++++++++++++++++++++++++++
1 file changed, 113 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 4643705021c6ca095a16d8d7cc3adac920b21e82..cea4df8b4673c938428ce1b6f3f5cc9e5be3d3ea 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8750-gcc.h>
#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
+#include <dt-bindings/clock/qcom,sm8750-videocc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
@@ -2581,6 +2582,118 @@ data-pins {
};
};
+ iris: video-codec@aa00000 {
+ compatible = "qcom,sm8750-iris";
+ reg = <0x0 0x0aa00000 0x0 0xf0000>;
+
+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+ <&videocc VIDEO_CC_MVS0C_CLK>,
+ <&videocc VIDEO_CC_MVS0_CLK>,
+ <&gcc GCC_VIDEO_AXI1_CLK>,
+ <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>,
+ <&videocc VIDEO_CC_MVS0_FREERUN_CLK>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core",
+ "iface1",
+ "core_freerun",
+ "vcodec0_core_freerun";
+
+ dma-coherent;
+ iommus = <&apps_smmu 0x1940 0>,
+ <&apps_smmu 0x1947 0>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ memory-region = <&video_mem>;
+
+ operating-points-v2 = <&iris_opp_table>;
+
+ power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
+ <&videocc VIDEO_CC_MVS0_GDSC>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_MMCX>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "mxc",
+ "mmcx";
+
+ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
+ <&gcc GCC_VIDEO_AXI1_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>;
+ reset-names = "bus0",
+ "bus1",
+ "core",
+ "vcodec0_core";
+
+ /*
+ * IRIS firmware is signed by vendors, only
+ * enable in boards where the proper signed firmware
+ * is available.
+ */
+ status = "disabled";
+
+ iris_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-240000000 {
+ opp-hz = /bits/ 64 <240000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>,
+ <&rpmhpd_opp_low_svs_d1>;
+ };
+
+ opp-338000000 {
+ opp-hz = /bits/ 64 <338000000>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-420000000 {
+ opp-hz = /bits/ 64 <420000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-533333334 {
+ opp-hz = /bits/ 64 <533333334>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_nom>;
+ };
+
+ opp-630000000 {
+ opp-hz = /bits/ 64 <630000000>;
+ required-opps = <&rpmhpd_opp_turbo>,
+ <&rpmhpd_opp_turbo>;
+ };
+ };
+ };
+
+ videocc: clock-controller@aaf0000 {
+ compatible = "qcom,sm8750-videocc";
+ reg = <0x0 0x0aaf0000 0x0 0x10000>;
+ clocks = <&bi_tcxo_div2>,
+ <&gcc GCC_VIDEO_AHB_CLK>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8750-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>;
--
2.48.1On 8/6/25 2:38 PM, Krzysztof Kozlowski wrote:
> Add Iris video codec to SM8750 SoC, which comes with significantly
> different powering up sequence than previous SM8650, thus different
> clocks and resets. For consistency keep existing clock and clock-names
> naming, so the list shares common part.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> ---
[...]
> + iris_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-240000000 {
> + opp-hz = /bits/ 64 <240000000>;
> + required-opps = <&rpmhpd_opp_low_svs_d1>,
> + <&rpmhpd_opp_low_svs_d1>;
> + };
> +
> + opp-338000000 {
> + opp-hz = /bits/ 64 <338000000>;
> + required-opps = <&rpmhpd_opp_low_svs>,
> + <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-420000000 {
> + opp-hz = /bits/ 64 <420000000>;
> + required-opps = <&rpmhpd_opp_svs>,
> + <&rpmhpd_opp_svs>;
> + };
> +
> + opp-444000000 {
> + opp-hz = /bits/ 64 <444000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>,
> + <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-533333334 {
> + opp-hz = /bits/ 64 <533333334>;
> + required-opps = <&rpmhpd_opp_nom>,
> + <&rpmhpd_opp_nom>;
> + };
There's an additional OPP: 570 MHz @ NOM_L1
+Dmitry, Vikash, please make sure you're OK with the iommu entries
the other properties look OK
Konrad
On Tue, Aug 12, 2025 at 04:21:12PM +0200, Konrad Dybcio wrote:
> On 8/6/25 2:38 PM, Krzysztof Kozlowski wrote:
> > Add Iris video codec to SM8750 SoC, which comes with significantly
> > different powering up sequence than previous SM8650, thus different
> > clocks and resets. For consistency keep existing clock and clock-names
> > naming, so the list shares common part.
> >
> > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> >
> > ---
>
> [...]
>
> > + iris_opp_table: opp-table {
> > + compatible = "operating-points-v2";
> > +
> > + opp-240000000 {
> > + opp-hz = /bits/ 64 <240000000>;
> > + required-opps = <&rpmhpd_opp_low_svs_d1>,
> > + <&rpmhpd_opp_low_svs_d1>;
> > + };
> > +
> > + opp-338000000 {
> > + opp-hz = /bits/ 64 <338000000>;
> > + required-opps = <&rpmhpd_opp_low_svs>,
> > + <&rpmhpd_opp_low_svs>;
> > + };
> > +
> > + opp-420000000 {
> > + opp-hz = /bits/ 64 <420000000>;
> > + required-opps = <&rpmhpd_opp_svs>,
> > + <&rpmhpd_opp_svs>;
> > + };
> > +
> > + opp-444000000 {
> > + opp-hz = /bits/ 64 <444000000>;
> > + required-opps = <&rpmhpd_opp_svs_l1>,
> > + <&rpmhpd_opp_svs_l1>;
> > + };
> > +
> > + opp-533333334 {
> > + opp-hz = /bits/ 64 <533333334>;
> > + required-opps = <&rpmhpd_opp_nom>,
> > + <&rpmhpd_opp_nom>;
> > + };
>
> There's an additional OPP: 570 MHz @ NOM_L1
>
> +Dmitry, Vikash, please make sure you're OK with the iommu entries
We still don't have a way to describe it other way at this point.
>
> the other properties look OK
>
> Konrad
--
With best wishes
Dmitry
On 8/12/2025 8:09 PM, Dmitry Baryshkov wrote:
> On Tue, Aug 12, 2025 at 04:21:12PM +0200, Konrad Dybcio wrote:
>> On 8/6/25 2:38 PM, Krzysztof Kozlowski wrote:
>>> Add Iris video codec to SM8750 SoC, which comes with significantly
>>> different powering up sequence than previous SM8650, thus different
>>> clocks and resets. For consistency keep existing clock and clock-names
>>> naming, so the list shares common part.
>>>
>>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>
>>> ---
>>
>> [...]
>>
>>> + iris_opp_table: opp-table {
>>> + compatible = "operating-points-v2";
>>> +
>>> + opp-240000000 {
>>> + opp-hz = /bits/ 64 <240000000>;
>>> + required-opps = <&rpmhpd_opp_low_svs_d1>,
>>> + <&rpmhpd_opp_low_svs_d1>;
>>> + };
>>> +
>>> + opp-338000000 {
>>> + opp-hz = /bits/ 64 <338000000>;
>>> + required-opps = <&rpmhpd_opp_low_svs>,
>>> + <&rpmhpd_opp_low_svs>;
>>> + };
>>> +
>>> + opp-420000000 {
>>> + opp-hz = /bits/ 64 <420000000>;
>>> + required-opps = <&rpmhpd_opp_svs>,
>>> + <&rpmhpd_opp_svs>;
>>> + };
>>> +
>>> + opp-444000000 {
>>> + opp-hz = /bits/ 64 <444000000>;
>>> + required-opps = <&rpmhpd_opp_svs_l1>,
>>> + <&rpmhpd_opp_svs_l1>;
>>> + };
>>> +
>>> + opp-533333334 {
>>> + opp-hz = /bits/ 64 <533333334>;
>>> + required-opps = <&rpmhpd_opp_nom>,
>>> + <&rpmhpd_opp_nom>;
>>> + };
>>
>> There's an additional OPP: 570 MHz @ NOM_L1
>>
>> +Dmitry, Vikash, please make sure you're OK with the iommu entries
>
> We still don't have a way to describe it other way at this point.
I could validate the extended "iommu-map-masks" proposal. Given that we have a
new binding for SM8750 [1] , does it make sense to add iommus min/max as [1,5] ?
such that later if new property is introduced "iommu-map-mask", it does not
break ABI.
iommus = <&apps_smmu 0x1940 0>;
iommu-map-masks = <0 &apps_smmu 0x1947 1 0>;
[1] https://lore.kernel.org/all/20250804-sm8750-iris-v2-1-6d78407f8078@linaro.org/
Regards,
Vikash
>
>>
>> the other properties look OK
>>
>> Konrad
>
On Tue, Aug 12, 2025 at 09:01:36PM +0530, Vikash Garodia wrote:
>
> On 8/12/2025 8:09 PM, Dmitry Baryshkov wrote:
> > On Tue, Aug 12, 2025 at 04:21:12PM +0200, Konrad Dybcio wrote:
> >> On 8/6/25 2:38 PM, Krzysztof Kozlowski wrote:
> >>> Add Iris video codec to SM8750 SoC, which comes with significantly
> >>> different powering up sequence than previous SM8650, thus different
> >>> clocks and resets. For consistency keep existing clock and clock-names
> >>> naming, so the list shares common part.
> >>>
> >>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> >>>
> >>> ---
> >>
> >> [...]
> >>
> >>> + iris_opp_table: opp-table {
> >>> + compatible = "operating-points-v2";
> >>> +
> >>> + opp-240000000 {
> >>> + opp-hz = /bits/ 64 <240000000>;
> >>> + required-opps = <&rpmhpd_opp_low_svs_d1>,
> >>> + <&rpmhpd_opp_low_svs_d1>;
> >>> + };
> >>> +
> >>> + opp-338000000 {
> >>> + opp-hz = /bits/ 64 <338000000>;
> >>> + required-opps = <&rpmhpd_opp_low_svs>,
> >>> + <&rpmhpd_opp_low_svs>;
> >>> + };
> >>> +
> >>> + opp-420000000 {
> >>> + opp-hz = /bits/ 64 <420000000>;
> >>> + required-opps = <&rpmhpd_opp_svs>,
> >>> + <&rpmhpd_opp_svs>;
> >>> + };
> >>> +
> >>> + opp-444000000 {
> >>> + opp-hz = /bits/ 64 <444000000>;
> >>> + required-opps = <&rpmhpd_opp_svs_l1>,
> >>> + <&rpmhpd_opp_svs_l1>;
> >>> + };
> >>> +
> >>> + opp-533333334 {
> >>> + opp-hz = /bits/ 64 <533333334>;
> >>> + required-opps = <&rpmhpd_opp_nom>,
> >>> + <&rpmhpd_opp_nom>;
> >>> + };
> >>
> >> There's an additional OPP: 570 MHz @ NOM_L1
> >>
> >> +Dmitry, Vikash, please make sure you're OK with the iommu entries
> >
> > We still don't have a way to describe it other way at this point.
>
> I could validate the extended "iommu-map-masks" proposal. Given that we have a
Was it posted? If not, let's get it ASAP.
> new binding for SM8750 [1] , does it make sense to add iommus min/max as [1,5] ?
Why [1, 5]? It should be [1, 2] or just [1, 1] + your proposal.
> such that later if new property is introduced "iommu-map-mask", it does not
> break ABI.
>
> iommus = <&apps_smmu 0x1940 0>;
> iommu-map-masks = <0 &apps_smmu 0x1947 1 0>;
>
> [1] https://lore.kernel.org/all/20250804-sm8750-iris-v2-1-6d78407f8078@linaro.org/
>
> Regards,
> Vikash
> >
> >>
> >> the other properties look OK
> >>
> >> Konrad
> >
--
With best wishes
Dmitry
On 8/14/2025 12:11 AM, Dmitry Baryshkov wrote:
> On Tue, Aug 12, 2025 at 09:01:36PM +0530, Vikash Garodia wrote:
>>
>> On 8/12/2025 8:09 PM, Dmitry Baryshkov wrote:
>>> On Tue, Aug 12, 2025 at 04:21:12PM +0200, Konrad Dybcio wrote:
>>>> On 8/6/25 2:38 PM, Krzysztof Kozlowski wrote:
>>>>> Add Iris video codec to SM8750 SoC, which comes with significantly
>>>>> different powering up sequence than previous SM8650, thus different
>>>>> clocks and resets. For consistency keep existing clock and clock-names
>>>>> naming, so the list shares common part.
>>>>>
>>>>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>>>
>>>>> ---
>>>>
>>>> [...]
>>>>
>>>>> + iris_opp_table: opp-table {
>>>>> + compatible = "operating-points-v2";
>>>>> +
>>>>> + opp-240000000 {
>>>>> + opp-hz = /bits/ 64 <240000000>;
>>>>> + required-opps = <&rpmhpd_opp_low_svs_d1>,
>>>>> + <&rpmhpd_opp_low_svs_d1>;
>>>>> + };
>>>>> +
>>>>> + opp-338000000 {
>>>>> + opp-hz = /bits/ 64 <338000000>;
>>>>> + required-opps = <&rpmhpd_opp_low_svs>,
>>>>> + <&rpmhpd_opp_low_svs>;
>>>>> + };
>>>>> +
>>>>> + opp-420000000 {
>>>>> + opp-hz = /bits/ 64 <420000000>;
>>>>> + required-opps = <&rpmhpd_opp_svs>,
>>>>> + <&rpmhpd_opp_svs>;
>>>>> + };
>>>>> +
>>>>> + opp-444000000 {
>>>>> + opp-hz = /bits/ 64 <444000000>;
>>>>> + required-opps = <&rpmhpd_opp_svs_l1>,
>>>>> + <&rpmhpd_opp_svs_l1>;
>>>>> + };
>>>>> +
>>>>> + opp-533333334 {
>>>>> + opp-hz = /bits/ 64 <533333334>;
>>>>> + required-opps = <&rpmhpd_opp_nom>,
>>>>> + <&rpmhpd_opp_nom>;
>>>>> + };
>>>>
>>>> There's an additional OPP: 570 MHz @ NOM_L1
>>>>
>>>> +Dmitry, Vikash, please make sure you're OK with the iommu entries
>>>
>>> We still don't have a way to describe it other way at this point.
>>
>> I could validate the extended "iommu-map-masks" proposal. Given that we have a
>
> Was it posted? If not, let's get it ASAP.
iommu-range (+Prakash) is a WIP, which is needed alognwith iommu-map-mask.
>
>> new binding for SM8750 [1] , does it make sense to add iommus min/max as [1,5] ?
>
> Why [1, 5]? It should be [1, 2] or just [1, 1] + your proposal.
[1,2] should be good for the iris device and remaining SIDs can be covered with
device allocated dynamically via iommu-map-mask proposal
>
>> such that later if new property is introduced "iommu-map-mask", it does not
>> break ABI.
>>
>> iommus = <&apps_smmu 0x1940 0>;
>> iommu-map-masks = <0 &apps_smmu 0x1947 1 0>;
>>
>> [1] https://lore.kernel.org/all/20250804-sm8750-iris-v2-1-6d78407f8078@linaro.org/
>>
>> Regards,
>> Vikash
>>>
>>>>
>>>> the other properties look OK
>>>>
>>>> Konrad
>>>
>
On 12/08/2025 16:21, Konrad Dybcio wrote:
> On 8/6/25 2:38 PM, Krzysztof Kozlowski wrote:
>> Add Iris video codec to SM8750 SoC, which comes with significantly
>> different powering up sequence than previous SM8650, thus different
>> clocks and resets. For consistency keep existing clock and clock-names
>> naming, so the list shares common part.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>
>> ---
>
> [...]
>
>> + iris_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-240000000 {
>> + opp-hz = /bits/ 64 <240000000>;
>> + required-opps = <&rpmhpd_opp_low_svs_d1>,
>> + <&rpmhpd_opp_low_svs_d1>;
>> + };
>> +
>> + opp-338000000 {
>> + opp-hz = /bits/ 64 <338000000>;
>> + required-opps = <&rpmhpd_opp_low_svs>,
>> + <&rpmhpd_opp_low_svs>;
>> + };
>> +
>> + opp-420000000 {
>> + opp-hz = /bits/ 64 <420000000>;
>> + required-opps = <&rpmhpd_opp_svs>,
>> + <&rpmhpd_opp_svs>;
>> + };
>> +
>> + opp-444000000 {
>> + opp-hz = /bits/ 64 <444000000>;
>> + required-opps = <&rpmhpd_opp_svs_l1>,
>> + <&rpmhpd_opp_svs_l1>;
>> + };
>> +
>> + opp-533333334 {
>> + opp-hz = /bits/ 64 <533333334>;
>> + required-opps = <&rpmhpd_opp_nom>,
>> + <&rpmhpd_opp_nom>;
>> + };
>
> There's an additional OPP: 570 MHz @ NOM_L1
>
> +Dmitry, Vikash, please make sure you're OK with the iommu entries
That opp has troubles with clock, so would need some fixed in videocc or
iris, AFAIK. Otherwise you will just PM OPP failures. I can add it
though, at the end DTS should be independent of drivers. :)
Best regards,
Krzysztof
On 8/12/25 4:24 PM, Krzysztof Kozlowski wrote:
> On 12/08/2025 16:21, Konrad Dybcio wrote:
>> On 8/6/25 2:38 PM, Krzysztof Kozlowski wrote:
>>> Add Iris video codec to SM8750 SoC, which comes with significantly
>>> different powering up sequence than previous SM8650, thus different
>>> clocks and resets. For consistency keep existing clock and clock-names
>>> naming, so the list shares common part.
>>>
>>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>
>>> ---
>>
>> [...]
>>
>>> + iris_opp_table: opp-table {
>>> + compatible = "operating-points-v2";
>>> +
>>> + opp-240000000 {
>>> + opp-hz = /bits/ 64 <240000000>;
>>> + required-opps = <&rpmhpd_opp_low_svs_d1>,
>>> + <&rpmhpd_opp_low_svs_d1>;
>>> + };
>>> +
>>> + opp-338000000 {
>>> + opp-hz = /bits/ 64 <338000000>;
>>> + required-opps = <&rpmhpd_opp_low_svs>,
>>> + <&rpmhpd_opp_low_svs>;
>>> + };
>>> +
>>> + opp-420000000 {
>>> + opp-hz = /bits/ 64 <420000000>;
>>> + required-opps = <&rpmhpd_opp_svs>,
>>> + <&rpmhpd_opp_svs>;
>>> + };
>>> +
>>> + opp-444000000 {
>>> + opp-hz = /bits/ 64 <444000000>;
>>> + required-opps = <&rpmhpd_opp_svs_l1>,
>>> + <&rpmhpd_opp_svs_l1>;
>>> + };
>>> +
>>> + opp-533333334 {
>>> + opp-hz = /bits/ 64 <533333334>;
>>> + required-opps = <&rpmhpd_opp_nom>,
>>> + <&rpmhpd_opp_nom>;
>>> + };
>>
>> There's an additional OPP: 570 MHz @ NOM_L1
>>
>> +Dmitry, Vikash, please make sure you're OK with the iommu entries
>
>
> That opp has troubles with clock, so would need some fixed in videocc or
> iris, AFAIK. Otherwise you will just PM OPP failures. I can add it
> though, at the end DTS should be independent of drivers. :)
Weird, there's an entry in the frequency table for it (well, * 3 the
rate) and it comes out of the same PLL as other ones.. what sort of
opp failures do you see?
Konrad
On 12/08/2025 16:26, Konrad Dybcio wrote:
> On 8/12/25 4:24 PM, Krzysztof Kozlowski wrote:
>> On 12/08/2025 16:21, Konrad Dybcio wrote:
>>> On 8/6/25 2:38 PM, Krzysztof Kozlowski wrote:
>>>> Add Iris video codec to SM8750 SoC, which comes with significantly
>>>> different powering up sequence than previous SM8650, thus different
>>>> clocks and resets. For consistency keep existing clock and clock-names
>>>> naming, so the list shares common part.
>>>>
>>>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>>
>>>> ---
>>>
>>> [...]
>>>
>>>> + iris_opp_table: opp-table {
>>>> + compatible = "operating-points-v2";
>>>> +
>>>> + opp-240000000 {
>>>> + opp-hz = /bits/ 64 <240000000>;
>>>> + required-opps = <&rpmhpd_opp_low_svs_d1>,
>>>> + <&rpmhpd_opp_low_svs_d1>;
>>>> + };
>>>> +
>>>> + opp-338000000 {
>>>> + opp-hz = /bits/ 64 <338000000>;
>>>> + required-opps = <&rpmhpd_opp_low_svs>,
>>>> + <&rpmhpd_opp_low_svs>;
>>>> + };
>>>> +
>>>> + opp-420000000 {
>>>> + opp-hz = /bits/ 64 <420000000>;
>>>> + required-opps = <&rpmhpd_opp_svs>,
>>>> + <&rpmhpd_opp_svs>;
>>>> + };
>>>> +
>>>> + opp-444000000 {
>>>> + opp-hz = /bits/ 64 <444000000>;
>>>> + required-opps = <&rpmhpd_opp_svs_l1>,
>>>> + <&rpmhpd_opp_svs_l1>;
>>>> + };
>>>> +
>>>> + opp-533333334 {
>>>> + opp-hz = /bits/ 64 <533333334>;
>>>> + required-opps = <&rpmhpd_opp_nom>,
>>>> + <&rpmhpd_opp_nom>;
>>>> + };
>>>
>>> There's an additional OPP: 570 MHz @ NOM_L1
>>>
>>> +Dmitry, Vikash, please make sure you're OK with the iommu entries
>>
>>
>> That opp has troubles with clock, so would need some fixed in videocc or
>> iris, AFAIK. Otherwise you will just PM OPP failures. I can add it
>> though, at the end DTS should be independent of drivers. :)
>
> Weird, there's an entry in the frequency table for it (well, * 3 the
> rate) and it comes out of the same PLL as other ones.. what sort of
You mean freq_tbl in P_VIDEO_CC_PLL0_OUT_MAIN? Yeah, I also saw that.
> opp failures do you see?
Only:
[ 9.306006] qcom-iris aa00000.video-codec: dev_pm_opp_set_rate:
failed to find OPP for freq 630000000 (-34)
[ 9.316078] qcom-iris aa00000.video-codec: power on failed
[ 9.322001] qcom-iris aa00000.video-codec: core init failed
Best regards,
Krzysztof
On 12/08/2025 16:39, Krzysztof Kozlowski wrote:
>>>>> +
>>>>> + opp-533333334 {
>>>>> + opp-hz = /bits/ 64 <533333334>;
>>>>> + required-opps = <&rpmhpd_opp_nom>,
>>>>> + <&rpmhpd_opp_nom>;
>>>>> + };
>>>>
>>>> There's an additional OPP: 570 MHz @ NOM_L1
>>>>
>>>> +Dmitry, Vikash, please make sure you're OK with the iommu entries
>>>
>>>
>>> That opp has troubles with clock, so would need some fixed in videocc or
>>> iris, AFAIK. Otherwise you will just PM OPP failures. I can add it
>>> though, at the end DTS should be independent of drivers. :)
>>
>> Weird, there's an entry in the frequency table for it (well, * 3 the
>> rate) and it comes out of the same PLL as other ones.. what sort of
>
> You mean freq_tbl in P_VIDEO_CC_PLL0_OUT_MAIN? Yeah, I also saw that.
>
>> opp failures do you see?
>
> Only:
>
> [ 9.306006] qcom-iris aa00000.video-codec: dev_pm_opp_set_rate:
> failed to find OPP for freq 630000000 (-34)
> [ 9.316078] qcom-iris aa00000.video-codec: power on failed
> [ 9.322001] qcom-iris aa00000.video-codec: core init failed
But I misunderstood you - I thought you want to replace 630, to match
downstream driver. If just added, then it's fine.
Best regards,
Krzysztof
On 12/08/2025 16:45, Krzysztof Kozlowski wrote: >>> Weird, there's an entry in the frequency table for it (well, * 3 the >>> rate) and it comes out of the same PLL as other ones.. what sort of >> >> You mean freq_tbl in P_VIDEO_CC_PLL0_OUT_MAIN? Yeah, I also saw that. >> >>> opp failures do you see? >> >> Only: >> >> [ 9.306006] qcom-iris aa00000.video-codec: dev_pm_opp_set_rate: >> failed to find OPP for freq 630000000 (-34) >> [ 9.316078] qcom-iris aa00000.video-codec: power on failed >> [ 9.322001] qcom-iris aa00000.video-codec: core init failed > > But I misunderstood you - I thought you want to replace 630, to match > downstream driver. If just added, then it's fine. ... and to confirm: it works and I double checked it now with frequency plans, so I will add missing 570. Best regards, Krzysztof
© 2016 - 2025 Red Hat, Inc.