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Wed, 06 Aug 2025 05:38:43 -0700 (PDT) From: Krzysztof Kozlowski Date: Wed, 06 Aug 2025 14:38:30 +0200 Subject: [PATCH RFC v2 1/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250806-b4-sm8750-iris-dts-v2-1-2ce197525eed@linaro.org> References: <20250806-b4-sm8750-iris-dts-v2-0-2ce197525eed@linaro.org> In-Reply-To: <20250806-b4-sm8750-iris-dts-v2-0-2ce197525eed@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4667; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=ckCBBYQJsML80sFucr4APIoykaSAsm3OKq2MQyMsH/g=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBok0zOt2M+enfTOT3YnWSwEyo61cZxEy4NyjuPu mwtu96tbgKJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaJNMzgAKCRDBN2bmhouD 18x3D/9MJFOcGVCQeEPv+J8d5nYLfy7VA76MSfT5o2pWIX5g1TAKjBtm2Jfvlpw89YvxQnk+fu5 NMwySyOckLl1juOT+rW/AeZWl95jxj/98nuN8VhLXaWbJIRrWt88m1qV+ro+jBzQQJFDcHF+yFM VCqOvYnrg/qJOwFvRYYtCZYjLAh0MUTcYU+5XKK6PRAEhr2LiJBmTcCUSoA0/G1ssq7NxiP0i6t k3Cw0HEpQITmluUSvhoH9/vxT5fcjpYQPAeSJzw8Bb16SS7XMAjXfUOn1rNzeZw1RTdnpechBnk L9pnp+Ui6y5ZR+yuG/R2E+tP1q6boEhqPIvvCpMopbs6HMe55zCiCNX9btkY4cYTDs2JuNMb1TY 47+MHZzsUNt3ihGehEWPwnY2GhCc0P/oh1KApjLtxQtJdGOdl9J2v+f0RIo0vsJ5BZd10bbXqM2 beshs2+bQY4/MzQBdQeEUGeDX+v/63yqho9vZJOl7xCT+RMAYfTu+94qNEe5gxXjcqg+Bv91r22 ogqaarq/xl2zRd/X5xTdgtfl4Ds45gZVb7PuKyPIzQZ8N6PPnxNsi29Rjp7wrKpKviyJYtShoKb v7V57r+nyLUkwoiWAbIQGCEVaEiP5b89MTehvDWbJ4vjZeI2N6wNl+GHm/yKAY+IbEFZ+qYFCPe Xqe3N8qUewnnTSg== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add Iris video codec to SM8750 SoC, which comes with significantly different powering up sequence than previous SM8650, thus different clocks and resets. For consistency keep existing clock and clock-names naming, so the list shares common part. Signed-off-by: Krzysztof Kozlowski --- qcom,sm8750-videocc bindings and clock headers dependency (will fail build): https://lore.kernel.org/all/20241206-sm8750_videocc-v1-0-5da6e7eea2bd@quici= nc.com/ qcom,sm8750-iris bindings: https://lore.kernel.org/r/20250804-sm8750-iris-v2-0-6d78407f8078@linaro.org --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 113 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 113 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index 4643705021c6ca095a16d8d7cc3adac920b21e82..cea4df8b4673c938428ce1b6f3f= 5cc9e5be3d3ea 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -2581,6 +2582,118 @@ data-pins { }; }; =20 + iris: video-codec@aa00000 { + compatible =3D "qcom,sm8750-iris"; + reg =3D <0x0 0x0aa00000 0x0 0xf0000>; + + clocks =3D <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>, + <&gcc GCC_VIDEO_AXI1_CLK>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK>; + clock-names =3D "iface", + "core", + "vcodec0_core", + "iface1", + "core_freerun", + "vcodec0_core_freerun"; + + dma-coherent; + iommus =3D <&apps_smmu 0x1940 0>, + <&apps_smmu 0x1947 0>; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "cpu-cfg", + "video-mem"; + + interrupts =3D ; + + memory-region =3D <&video_mem>; + + operating-points-v2 =3D <&iris_opp_table>; + + power-domains =3D <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names =3D "venus", + "vcodec0", + "mxc", + "mmcx"; + + resets =3D <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&gcc GCC_VIDEO_AXI1_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>; + reset-names =3D "bus0", + "bus1", + "core", + "vcodec0_core"; + + /* + * IRIS firmware is signed by vendors, only + * enable in boards where the proper signed firmware + * is available. + */ + status =3D "disabled"; + + iris_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-240000000 { + opp-hz =3D /bits/ 64 <240000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs_d1>; + }; + + opp-338000000 { + opp-hz =3D /bits/ 64 <338000000>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-420000000 { + opp-hz =3D /bits/ 64 <420000000>; + required-opps =3D <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-444000000 { + opp-hz =3D /bits/ 64 <444000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-533333334 { + opp-hz =3D /bits/ 64 <533333334>; + required-opps =3D <&rpmhpd_opp_nom>, + <&rpmhpd_opp_nom>; + }; + + opp-630000000 { + opp-hz =3D /bits/ 64 <630000000>; + required-opps =3D <&rpmhpd_opp_turbo>, + <&rpmhpd_opp_turbo>; + }; + }; + }; + + videocc: clock-controller@aaf0000 { + compatible =3D "qcom,sm8750-videocc"; + reg =3D <0x0 0x0aaf0000 0x0 0x10000>; + clocks =3D <&bi_tcxo_div2>, + <&gcc GCC_VIDEO_AHB_CLK>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,sm8750-pdc", "qcom,pdc"; reg =3D <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; --=20 2.48.1