This series adds the MDSS, DPU and DPTX0 node on Qualcomm QCS8300 SoC.
It also enables Display Port on Qualcomm QCS8300-ride platform.
Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com>
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This series make top of 3 dt-bindings
https://lore.kernel.org/all/20250717-dp_mst_bindings-v3-0-72ce08285703@oss.qualcomm.com/
https://lore.kernel.org/all/20250730072725.1433360-1-quic_yongmou@quicinc.com/
https://lore.kernel.org/all/20250730-mdssdt_qcs8300-v5-0-bc8ea35bbed6@quicinc.com/
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Changes in v4:Fixed review comments from Krzysztof.
- Add the 4 pixel stream register regions and the correspondings clocks of the DP controller.
- Change DP controlller compatible to qcs8300-dp.
- Rebase to next-20250717.
- Link to v3: https://lore.kernel.org/r/20250114-dts_qcs8300-v3-0-d114cc5e4af9@quicinc.com
Changes in v3:Fixed review comments from Konrad, Dmitry.
- Correct the Power-domain for DP PHY should be
RPMHPD_MX.[Dmitry][Konrad]
- Correct the interconnects path for mdp and align the property order
with x1e80100.dtsi.[Konrad]
- Rebase the patch to latest code base and update the dependencies in
the cover letter.
- Link to v2: https://lore.kernel.org/r/20241226-dts_qcs8300-v2-0-ec8d4fb65cba@quicinc.com
Changes in v2:Fixed review comments from Konrad, Dmitry and Krzysztof.
- Reuse eDP PHY and DPU of SA8775 Platform.[Dmitry][Krzysztof]
- Reuse DisplayPort controller of SM8650.[Dmitry]
- Correct the regs length, format issues and power-domains.[Konrad]
- Integrate the dt changes of DPU and DP together.
- Link to v1: https://lore.kernel.org/all/20241127-dp_dts_qcs8300-v1-0-e3d13dec4233@quicinc.com/
~
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Yongxing Mou (2):
arm64: dts: qcom: qcs8300: add display dt nodes for MDSS, DPU, DisplayPort and eDP PHY
arm64: dts: qcom: qcs8300-ride: Enable Display Port
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 42 ++++++
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 216 +++++++++++++++++++++++++++++-
2 files changed, 257 insertions(+), 1 deletion(-)
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base-commit: 024e09e444bd2b06aee9d1f3fe7b313c7a2df1bb
change-id: 20241225-dts_qcs8300-4d4299067306
prerequisite-message-id: <20250113-dpphy_qcs9300-v1-1-842798ceee78@quicinc.com>
prerequisite-patch-id: 2ea89bba3c9c6ba37250ebd947c1d4acedc78a5d
prerequisite-message-id: <20250113-mdssdt_qcs8300-v3-0-6c8e93459600@quicinc.com>
prerequisite-patch-id: b798711c6a9bd9c4f0b692835865235e78cd2adb
prerequisite-patch-id: 146c61567c42bf5268d1005f8e9b307ea2af93d9
prerequisite-patch-id: 3ce5246ad3470d7392df23a52b3c8b8bd1662db6
prerequisite-patch-id: e81de8a09467a49eaeb4af73a0e197e4156ce202
prerequisite-message-id: <20250717-dp_mst_bindings-v3-0-72ce08285703@oss.qualcomm.com>
prerequisite-patch-id: 4782272bb7d2403e2f2dbf762586d4570e6b6ba6
prerequisite-patch-id: cfdd5c37d38b2a4f1386af4021ba3920c6d8dcf8
prerequisite-patch-id: c874bf64aec8cb2ff0bc91051620ac771cbeeeea
prerequisite-patch-id: 63defbfb812a2f9c6365a98538421aea374e0e13
prerequisite-patch-id: 0ffa9d544d516d4e14700229a4ab6a9c7751823f
Best regards,
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Yongxing Mou <quic_yongmou@quicinc.com>