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Signed-off-by: Yongxing Mou --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 216 ++++++++++++++++++++++++++++++= +++- 1 file changed, 215 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qc= om/qcs8300.dtsi index 7ada029c32c1f2d0488a3fd1be603887c64bf4f9..93797696c72a2001dc0564454da= 281745f0a7433 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -4308,6 +4308,218 @@ camcc: clock-controller@ade0000 { #power-domain-cells =3D <1>; }; =20 + mdss: display-subsystem@ae00000 { + compatible =3D "qcom,qcs8300-mdss"; + reg =3D <0x0 0x0ae00000 0x0 0x1000>; + reg-names =3D "mdss"; + + interrupts =3D ; + + clocks =3D <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>; + + resets =3D <&dispcc MDSS_DISP_CC_MDSS_CORE_BCR>; + + interconnects =3D <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + power-domains =3D <&dispcc MDSS_DISP_CC_MDSS_CORE_GDSC>; + + iommus =3D <&apps_smmu 0x1000 0x402>; + + interrupt-controller; + #interrupt-cells =3D <1>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible =3D "qcom,qcs8300-dpu", "qcom,sa8775p-dpu"; + reg =3D <0x0 0x0ae01000 0x0 0x8f000>, + <0x0 0x0aeb0000 0x0 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu_intf0_out: endpoint { + remote-endpoint =3D <&mdss_dp0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-375000000 { + opp-hz =3D /bits/ 64 <375000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz =3D /bits/ 64 <575000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + }; + + opp-650000000 { + opp-hz =3D /bits/ 64 <650000000>; + required-opps =3D <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + mdss_dp0_phy: phy@aec2a00 { + compatible =3D "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy"; + + reg =3D <0x0 0x0aec2a00 0x0 0x19c>, + <0x0 0x0aec2200 0x0 0xec>, + <0x0 0x0aec2600 0x0 0xec>, + <0x0 0x0aec2000 0x0 0x1c8>; + + clocks =3D <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>; + clock-names =3D "aux", + "cfg_ahb"; + + power-domains =3D <&rpmhpd RPMHPD_MX>; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + mdss_dp0: displayport-controller@af54000 { + compatible =3D "qcom,qcs8300-dp"; + + reg =3D <0x0 0x0af54000 0x0 0x200>, + <0x0 0x0af54200 0x0 0x200>, + <0x0 0x0af55000 0x0 0xc00>, + <0x0 0x0af56000 0x0 0x400>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <12>; + + clocks =3D <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; + assigned-clocks =3D <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dp0_phy 0>, + <&mdss_dp0_phy 1>, + <&mdss_dp0_phy 1>, + <&mdss_dp0_phy 1>; + phys =3D <&mdss_dp0_phy>; + phy-names =3D "dp"; + + operating-points-v2 =3D <&dp_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + #sound-dai-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dp0_in: endpoint { + remote-endpoint =3D <&dpu_intf0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dp0_out: endpoint { }; + }; + }; + + dp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-160000000 { + opp-hz =3D /bits/ 64 <160000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + required-opps =3D <&rpmhpd_opp_nom>; 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Signed-off-by: Yongxing Mou --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 42 +++++++++++++++++++++++++++= ++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dt= s/qcom/qcs8300-ride.dts index 8c166ead912c589c01d2bc7d13fa1b6892f6252b..1ce4a3138eac45147eacf5fde8a= 7eaa79a9af9b1 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -23,6 +23,18 @@ chosen { stdout-path =3D "serial0:115200n8"; }; =20 + dp0-connector { + compatible =3D "dp-connector"; + label =3D "DP0"; + type =3D "full-size"; + + port { + dp0_connector_in: endpoint { + remote-endpoint =3D <&mdss_dp0_out>; + }; + }; + }; + regulator-usb2-vbus { compatible =3D "regulator-fixed"; regulator-name =3D "USB2_VBUS"; @@ -308,6 +320,30 @@ &iris { status =3D "okay"; }; =20 +&mdss { + status =3D "okay"; +}; + +&mdss_dp0 { + pinctrl-0 =3D <&dp_hot_plug_det>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&mdss_dp0_out { + data-lanes =3D <0 1 2 3>; + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000 81000000= 00>; + remote-endpoint =3D <&dp0_connector_in>; +}; + +&mdss_dp0_phy { + vdda-phy-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l4a>; + + status =3D "okay"; +}; + &qupv3_id_0 { status =3D "okay"; }; @@ -333,6 +369,12 @@ &serdes0 { }; =20 &tlmm { + dp_hot_plug_det: dp-hot-plug-det-state { + pins =3D "gpio94"; + function =3D "edp0_hot"; + bias-disable; + }; + ethernet0_default: ethernet0-default-state { ethernet0_mdc: ethernet0-mdc-pins { pins =3D "gpio5"; --=20 2.34.1