Add bindings documentation for the Glymur TCSR Clock Controller.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
.../bindings/clock/qcom,sm8550-tcsr.yaml | 3 +++
include/dt-bindings/clock/qcom,glymur-tcsr.h | 24 ++++++++++++++++++++++
2 files changed, 27 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
index f3afbb25e8682de83fb16acaa35448545f77ce77..9fbf8883678245b20d99c13cd1a7cd8c0feee11b 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
@@ -8,12 +8,14 @@ title: Qualcomm TCSR Clock Controller on SM8550
maintainers:
- Bjorn Andersson <andersson@kernel.org>
+ - Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm TCSR clock control module provides the clocks, resets and
power domains on SM8550
See also:
+ - include/dt-bindings/clock/qcom,glymur-tcsr.h
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
- include/dt-bindings/clock/qcom,sm8650-tcsr.h
- include/dt-bindings/clock/qcom,sm8750-tcsr.h
@@ -22,6 +24,7 @@ properties:
compatible:
items:
- enum:
+ - qcom,glymur-tcsr
- qcom,sar2130p-tcsr
- qcom,sm8550-tcsr
- qcom,sm8650-tcsr
diff --git a/include/dt-bindings/clock/qcom,glymur-tcsr.h b/include/dt-bindings/clock/qcom,glymur-tcsr.h
new file mode 100644
index 0000000000000000000000000000000000000000..72614226b113bb60f1e430fc18e13c46c8b043d3
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,glymur-tcsr.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_GLYMUR_H
+#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_GLYMUR_H
+
+/* TCSR_CC clocks */
+#define TCSR_EDP_CLKREF_EN 0
+#define TCSR_PCIE_1_CLKREF_EN 1
+#define TCSR_PCIE_2_CLKREF_EN 2
+#define TCSR_PCIE_3_CLKREF_EN 3
+#define TCSR_PCIE_4_CLKREF_EN 4
+#define TCSR_USB2_1_CLKREF_EN 5
+#define TCSR_USB2_2_CLKREF_EN 6
+#define TCSR_USB2_3_CLKREF_EN 7
+#define TCSR_USB2_4_CLKREF_EN 8
+#define TCSR_USB3_0_CLKREF_EN 9
+#define TCSR_USB3_1_CLKREF_EN 10
+#define TCSR_USB4_1_CLKREF_EN 11
+#define TCSR_USB4_2_CLKREF_EN 12
+
+#endif
--
2.34.1On Tue, Jul 29, 2025 at 11:12:36AM +0530, Taniya Das wrote: > Add bindings documentation for the Glymur TCSR Clock Controller. Same question as for v1, what is Glymur? Where is any DTS using this (or explanation of lack of DTS)? Best regards, Krzysztof
On 7/30/2025 12:47 PM, Krzysztof Kozlowski wrote: > On Tue, Jul 29, 2025 at 11:12:36AM +0530, Taniya Das wrote: >> Add bindings documentation for the Glymur TCSR Clock Controller. > > Same question as for v1, what is Glymur? Glymur is the Qualcomm's next gen compute SoC. > > Where is any DTS using this (or explanation of lack of DTS)? > Krzysztof, the DTS will be posted separately once the driver and bindings are reviewed. > Best regards, > Krzysztof > -- Thanks, Taniya Das
On Fri, Aug 01, 2025 at 09:44:47AM +0530, Taniya Das wrote: > > > On 7/30/2025 12:47 PM, Krzysztof Kozlowski wrote: > > On Tue, Jul 29, 2025 at 11:12:36AM +0530, Taniya Das wrote: > >> Add bindings documentation for the Glymur TCSR Clock Controller. > > > > Same question as for v1, what is Glymur? > > Glymur is the Qualcomm's next gen compute SoC. This question means that the 'Glymur' name should be explained in the commit message / cover letter. > > > > > Where is any DTS using this (or explanation of lack of DTS)? > > > > Krzysztof, the DTS will be posted separately once the driver and > bindings are reviewed. Same here. > > > > Best regards, > > Krzysztof > > > > -- > Thanks, > Taniya Das > -- With best wishes Dmitry
On 01/08/2025 06:14, Taniya Das wrote: > > > On 7/30/2025 12:47 PM, Krzysztof Kozlowski wrote: >> On Tue, Jul 29, 2025 at 11:12:36AM +0530, Taniya Das wrote: >>> Add bindings documentation for the Glymur TCSR Clock Controller. >> >> Same question as for v1, what is Glymur? > > Glymur is the Qualcomm's next gen compute SoC. Explain it in at least one commit msg, not in reply to me. > >> >> Where is any DTS using this (or explanation of lack of DTS)? >> > > Krzysztof, the DTS will be posted separately once the driver and > bindings are reviewed. Hm? That's not what I was told thus I ask. I am sure that above is not true, but if you insist and put it that way it is incorrect. You cannot send DTS because you wait with drivers to be reviewed. We want to see entire picture. Best regards, Krzysztof
On 8/1/2025 2:40 PM, Krzysztof Kozlowski wrote: > On 01/08/2025 06:14, Taniya Das wrote: >> >> >> On 7/30/2025 12:47 PM, Krzysztof Kozlowski wrote: >>> On Tue, Jul 29, 2025 at 11:12:36AM +0530, Taniya Das wrote: >>>> Add bindings documentation for the Glymur TCSR Clock Controller. >>> >>> Same question as for v1, what is Glymur? >> >> Glymur is the Qualcomm's next gen compute SoC. > > Explain it in at least one commit msg, not in reply to me. > Yes, I will add it in the next patch set. >> >>> >>> Where is any DTS using this (or explanation of lack of DTS)? >>> >> >> Krzysztof, the DTS will be posted separately once the driver and >> bindings are reviewed. > > Hm? That's not what I was told thus I ask. I am sure that above is not > true, but if you insist and put it that way it is incorrect. You cannot > send DTS because you wait with drivers to be reviewed. We want to see > entire picture. > > Best regards, > Krzysztof -- Thanks, Taniya Das
On 8/1/2025 2:40 PM, Krzysztof Kozlowski wrote: > On 01/08/2025 06:14, Taniya Das wrote: >> >> >> On 7/30/2025 12:47 PM, Krzysztof Kozlowski wrote: >>> On Tue, Jul 29, 2025 at 11:12:36AM +0530, Taniya Das wrote: >>>> Add bindings documentation for the Glymur TCSR Clock Controller. >>> >>> Same question as for v1, what is Glymur? >> >> Glymur is the Qualcomm's next gen compute SoC. > > Explain it in at least one commit msg, not in reply to me. > Yes, I will explain it in my next patchset. >> >>> >>> Where is any DTS using this (or explanation of lack of DTS)? >>> >> >> Krzysztof, the DTS will be posted separately once the driver and >> bindings are reviewed. > > Hm? That's not what I was told thus I ask. I am sure that above is not > true, but if you insist and put it that way it is incorrect. You cannot > send DTS because you wait with drivers to be reviewed. We want to see > entire picture. > Sorry for the confusion, Krzysztof. What I meant to convey is that we plan to post the DTS after the public announcement of the SoC, which is expected to happen within the next couple of months. In the meantime, we’re hoping to get the code reviewed. -- Thanks, Taniya Das
On 06/08/2025 11:57, Taniya Das wrote: > > Sorry for the confusion, Krzysztof. What I meant to convey is that we > plan to post the DTS after the public announcement of the SoC, which is > expected to happen within the next couple of months. In the meantime, > we’re hoping to get the code reviewed. Thanks, please briefly mention it in the cover letter. Best regards, Krzysztof
© 2016 - 2025 Red Hat, Inc.