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Mon, 28 Jul 2025 22:42:53 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFuyijweDxrMiwgBqN/idRldkyPp8drzrqj6AfWgmXdWv7KrRn2IrpZsZxZOMXJWFqdnEi80g== X-Received: by 2002:a17:903:22c1:b0:240:2610:a057 with SMTP id d9443c01a7336-2402610a284mr76973435ad.0.1753767772540; Mon, 28 Jul 2025 22:42:52 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23fe9b67485sm54505235ad.47.2025.07.28.22.42.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Jul 2025 22:42:52 -0700 (PDT) From: Taniya Das Date: Tue, 29 Jul 2025 11:12:36 +0530 Subject: [PATCH v3 2/7] dt-bindings: clock: qcom: Document the Glymur TCSR Clock Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250729-glymur-gcc-tcsrcc-rpmhcc-v3-2-227cfe5c8ef4@oss.qualcomm.com> References: <20250729-glymur-gcc-tcsrcc-rpmhcc-v3-0-227cfe5c8ef4@oss.qualcomm.com> In-Reply-To: <20250729-glymur-gcc-tcsrcc-rpmhcc-v3-0-227cfe5c8ef4@oss.qualcomm.com> To: kernel@oss.qualcomm.com, Pankaj Patil , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-ORIG-GUID: 8YR2P3f3ijz_EDQdMzxkyDM_zSlifQi3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI5MDAzOSBTYWx0ZWRfX03+fvYyaFi74 WcgB02QSZFxhAdMjIRdeomoPa+8BrLKngPeV85pbmy4wQxGcBMDTHLvme47EME9DCnLymsQAZ5j jWdlr5VNEzQAWncNhB8nHe2dJsNypZuFtZtjyEFV6SPb1d1Uw4b0IcsFfEeo40yOflfi7d1vRT/ qtsbJMFAq96Yb8Sv3H6xzhg4MP7iHh21BA87pDMl48hl+OGmlVScivN/ltIx0OJm84PAelvJx1T 8/fvjnICh8inDn2AvJetHKl2HihkJdR+KbDMyEsh04pYNArJOWgViPxjExMZo+NbeRBptko7rUq Mnfdf6xMX0Ob6zAxqaMpdEuUF85Ndg+K0uV52J21MxQIfWSXGkjli3LYccVM/lDxOREOUnh1iBH gsV3BCxk35ldL1812LhiFFTOgNqgh4hY2nHdDmqQjBcZyNrODMvzWdfBG3f3sy9jDTVlFwUE X-Proofpoint-GUID: 8YR2P3f3ijz_EDQdMzxkyDM_zSlifQi3 X-Authority-Analysis: v=2.4 cv=KtNN2XWN c=1 sm=1 tr=0 ts=68885f5f cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=NoBSHRPQAjGLFGKXj-wA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-29_01,2025-07-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 suspectscore=0 adultscore=0 mlxlogscore=999 bulkscore=0 spamscore=0 impostorscore=0 mlxscore=0 malwarescore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507290039 Add bindings documentation for the Glymur TCSR Clock Controller. Signed-off-by: Taniya Das --- .../bindings/clock/qcom,sm8550-tcsr.yaml | 3 +++ include/dt-bindings/clock/qcom,glymur-tcsr.h | 24 ++++++++++++++++++= ++++ 2 files changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml = b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml index f3afbb25e8682de83fb16acaa35448545f77ce77..9fbf8883678245b20d99c13cd1a= 7cd8c0feee11b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -8,12 +8,14 @@ title: Qualcomm TCSR Clock Controller on SM8550 =20 maintainers: - Bjorn Andersson + - Taniya Das =20 description: | Qualcomm TCSR clock control module provides the clocks, resets and power domains on SM8550 =20 See also: + - include/dt-bindings/clock/qcom,glymur-tcsr.h - include/dt-bindings/clock/qcom,sm8550-tcsr.h - include/dt-bindings/clock/qcom,sm8650-tcsr.h - include/dt-bindings/clock/qcom,sm8750-tcsr.h @@ -22,6 +24,7 @@ properties: compatible: items: - enum: + - qcom,glymur-tcsr - qcom,sar2130p-tcsr - qcom,sm8550-tcsr - qcom,sm8650-tcsr diff --git a/include/dt-bindings/clock/qcom,glymur-tcsr.h b/include/dt-bind= ings/clock/qcom,glymur-tcsr.h new file mode 100644 index 0000000000000000000000000000000000000000..72614226b113bb60f1e430fc18e= 13c46c8b043d3 --- /dev/null +++ b/include/dt-bindings/clock/qcom,glymur-tcsr.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_GLYMUR_H +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_GLYMUR_H + +/* TCSR_CC clocks */ +#define TCSR_EDP_CLKREF_EN 0 +#define TCSR_PCIE_1_CLKREF_EN 1 +#define TCSR_PCIE_2_CLKREF_EN 2 +#define TCSR_PCIE_3_CLKREF_EN 3 +#define TCSR_PCIE_4_CLKREF_EN 4 +#define TCSR_USB2_1_CLKREF_EN 5 +#define TCSR_USB2_2_CLKREF_EN 6 +#define TCSR_USB2_3_CLKREF_EN 7 +#define TCSR_USB2_4_CLKREF_EN 8 +#define TCSR_USB3_0_CLKREF_EN 9 +#define TCSR_USB3_1_CLKREF_EN 10 +#define TCSR_USB4_1_CLKREF_EN 11 +#define TCSR_USB4_2_CLKREF_EN 12 + +#endif --=20 2.34.1