arch/arm64/boot/dts/qcom/sm8650.dtsi | 414 +++++++++++++-------------- 1 file changed, 207 insertions(+), 207 deletions(-)
Qualcomm DTS uses sorting of MMIO nodes by the unit address, so move
few nodes in SM8650 DTSI to fix that.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 414 +++++++++++++--------------
1 file changed, 207 insertions(+), 207 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index e14d3d778b71..2360d560dc86 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -3490,6 +3490,11 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
};
};
+ rng: rng@10c3000 {
+ compatible = "qcom,sm8650-trng", "qcom,trng";
+ reg = <0 0x010c3000 0 0x1000>;
+ };
+
cnoc_main: interconnect@1500000 {
compatible = "qcom,sm8650-cnoc-main";
reg = <0 0x01500000 0 0x14080>;
@@ -3561,11 +3566,6 @@ mmss_noc: interconnect@1780000 {
#interconnect-cells = <2>;
};
- rng: rng@10c3000 {
- compatible = "qcom,sm8650-trng", "qcom,trng";
- reg = <0 0x010c3000 0 0x1000>;
- };
-
pcie0: pcie@1c00000 {
device_type = "pci";
compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
@@ -3926,38 +3926,6 @@ pcie1_phy: phy@1c0e000 {
status = "disabled";
};
- cryptobam: dma-controller@1dc4000 {
- compatible = "qcom,bam-v1.7.0";
- reg = <0 0x01dc4000 0 0x28000>;
-
- interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>;
-
- #dma-cells = <1>;
-
- iommus = <&apps_smmu 0x480 0>,
- <&apps_smmu 0x481 0>;
-
- qcom,ee = <0>;
- qcom,num-ees = <4>;
- num-channels = <20>;
- qcom,controlled-remotely;
- };
-
- crypto: crypto@1dfa000 {
- compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce";
- reg = <0 0x01dfa000 0 0x6000>;
-
- interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "memory";
-
- dmas = <&cryptobam 4>, <&cryptobam 5>;
- dma-names = "rx", "tx";
-
- iommus = <&apps_smmu 0x480 0>,
- <&apps_smmu 0x481 0>;
- };
-
ufs_mem_phy: phy@1d80000 {
compatible = "qcom,sm8650-qmp-ufs-phy";
reg = <0 0x01d80000 0 0x2000>;
@@ -4079,6 +4047,38 @@ ice: crypto@1d88000 {
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
};
+ cryptobam: dma-controller@1dc4000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0 0x01dc4000 0 0x28000>;
+
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ #dma-cells = <1>;
+
+ iommus = <&apps_smmu 0x480 0>,
+ <&apps_smmu 0x481 0>;
+
+ qcom,ee = <0>;
+ qcom,num-ees = <4>;
+ num-channels = <20>;
+ qcom,controlled-remotely;
+ };
+
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce";
+ reg = <0 0x01dfa000 0 0x6000>;
+
+ interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "memory";
+
+ dmas = <&cryptobam 4>, <&cryptobam 5>;
+ dma-names = "rx", "tx";
+
+ iommus = <&apps_smmu 0x480 0>,
+ <&apps_smmu 0x481 0>;
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0 0x01f40000 0 0x20000>;
@@ -4962,6 +4962,176 @@ opp-202000000 {
};
};
+ usb_1_hsphy: phy@88e3000 {
+ compatible = "qcom,sm8650-snps-eusb2-phy",
+ "qcom,sm8550-snps-eusb2-phy";
+ reg = <0 0x088e3000 0 0x154>;
+
+ clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_dp_qmpphy: phy@88e8000 {
+ compatible = "qcom,sm8650-qmp-usb3-dp-phy";
+ reg = <0 0x088e8000 0 0x3000>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "usb3_pipe";
+
+ resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
+ reset-names = "phy",
+ "common";
+
+ power-domains = <&gcc USB3_PHY_GDSC>;
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ orientation-switch;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_dp_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_dp_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_dp_qmpphy_dp_in: endpoint {
+ remote-endpoint = <&mdss_dp0_out>;
+ };
+ };
+ };
+ };
+
+ usb_1: usb@a6f8800 {
+ compatible = "qcom,sm8650-dwc3", "qcom,dwc3";
+ reg = <0 0x0a6f8800 0 0x400>;
+
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&pdc 14 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 15 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&tcsr TCSR_USB3_CLKREF_EN>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "xo";
+
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "usb-ddr",
+ "apps-usb";
+
+ power-domains = <&gcc USB30_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ usb_1_dwc3: usb@a600000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x0a600000 0 0xcd00>;
+
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ iommus = <&apps_smmu 0x40 0>;
+
+ phys = <&usb_1_hsphy>,
+ <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,usb2-gadget-lpm-disable;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,is-utmi-l1-suspend;
+ snps,usb3_lpm_capable;
+ snps,usb2-lpm-disable;
+ snps,has-lpm-erratum;
+ tx-fifo-resize;
+
+ dma-coherent;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
+ };
+ };
+ };
+ };
+ };
+
iris: video-codec@aa00000 {
compatible = "qcom,sm8650-iris";
reg = <0 0x0aa00000 0 0xf0000>;
@@ -5580,176 +5750,6 @@ dispcc: clock-controller@af00000 {
#power-domain-cells = <1>;
};
- usb_1_hsphy: phy@88e3000 {
- compatible = "qcom,sm8650-snps-eusb2-phy",
- "qcom,sm8550-snps-eusb2-phy";
- reg = <0 0x088e3000 0 0x154>;
-
- clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
- clock-names = "ref";
-
- resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
-
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- usb_dp_qmpphy: phy@88e8000 {
- compatible = "qcom,sm8650-qmp-usb3-dp-phy";
- reg = <0 0x088e8000 0 0x3000>;
-
- clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
- <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
- clock-names = "aux",
- "ref",
- "com_aux",
- "usb3_pipe";
-
- resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
- <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
- reset-names = "phy",
- "common";
-
- power-domains = <&gcc USB3_PHY_GDSC>;
-
- #clock-cells = <1>;
- #phy-cells = <1>;
-
- orientation-switch;
-
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- usb_dp_qmpphy_out: endpoint {
- };
- };
-
- port@1 {
- reg = <1>;
-
- usb_dp_qmpphy_usb_ss_in: endpoint {
- remote-endpoint = <&usb_1_dwc3_ss>;
- };
- };
-
- port@2 {
- reg = <2>;
-
- usb_dp_qmpphy_dp_in: endpoint {
- remote-endpoint = <&mdss_dp0_out>;
- };
- };
- };
- };
-
- usb_1: usb@a6f8800 {
- compatible = "qcom,sm8650-dwc3", "qcom,dwc3";
- reg = <0 0x0a6f8800 0 0x400>;
-
- interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,
- <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
- <&pdc 14 IRQ_TYPE_EDGE_RISING>,
- <&pdc 15 IRQ_TYPE_EDGE_RISING>,
- <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "pwr_event",
- "hs_phy_irq",
- "dp_hs_phy_irq",
- "dm_hs_phy_irq",
- "ss_phy_irq";
-
- clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
- <&gcc GCC_USB30_PRIM_MASTER_CLK>,
- <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
- <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
- <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
- <&tcsr TCSR_USB3_CLKREF_EN>;
- clock-names = "cfg_noc",
- "core",
- "iface",
- "sleep",
- "mock_utmi",
- "xo";
-
- assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
- <&gcc GCC_USB30_PRIM_MASTER_CLK>;
- assigned-clock-rates = <19200000>, <200000000>;
-
- resets = <&gcc GCC_USB30_PRIM_BCR>;
-
- interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
- &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
- interconnect-names = "usb-ddr",
- "apps-usb";
-
- power-domains = <&gcc USB30_PRIM_GDSC>;
- required-opps = <&rpmhpd_opp_nom>;
-
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- status = "disabled";
-
- usb_1_dwc3: usb@a600000 {
- compatible = "snps,dwc3";
- reg = <0 0x0a600000 0 0xcd00>;
-
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>;
-
- iommus = <&apps_smmu 0x40 0>;
-
- phys = <&usb_1_hsphy>,
- <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
- phy-names = "usb2-phy",
- "usb3-phy";
-
- snps,hird-threshold = /bits/ 8 <0x0>;
- snps,usb2-gadget-lpm-disable;
- snps,dis_u2_susphy_quirk;
- snps,dis_enblslpm_quirk;
- snps,dis-u1-entry-quirk;
- snps,dis-u2-entry-quirk;
- snps,is-utmi-l1-suspend;
- snps,usb3_lpm_capable;
- snps,usb2-lpm-disable;
- snps,has-lpm-erratum;
- tx-fifo-resize;
-
- dma-coherent;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- usb_1_dwc3_hs: endpoint {
- };
- };
-
- port@1 {
- reg = <1>;
-
- usb_1_dwc3_ss: endpoint {
- remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
- };
- };
- };
- };
- };
-
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8650-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
--
2.48.1
On Sun, 27 Jul 2025 21:36:53 +0200, Krzysztof Kozlowski wrote:
> Qualcomm DTS uses sorting of MMIO nodes by the unit address, so move
> few nodes in SM8650 DTSI to fix that.
>
>
Applied, thanks!
[1/1] arm64: dts: qcom: sm8650: Sort nodes by unit address
commit: 8def31f8c1e1f3d28e4ee3dcf6818a74c9a9a2f7
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
On 27/07/2025 21:36, Krzysztof Kozlowski wrote:
> Qualcomm DTS uses sorting of MMIO nodes by the unit address, so move
> few nodes in SM8650 DTSI to fix that.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 414 +++++++++++++--------------
> 1 file changed, 207 insertions(+), 207 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index e14d3d778b71..2360d560dc86 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -3490,6 +3490,11 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> };
> };
>
> + rng: rng@10c3000 {
> + compatible = "qcom,sm8650-trng", "qcom,trng";
> + reg = <0 0x010c3000 0 0x1000>;
> + };
> +
> cnoc_main: interconnect@1500000 {
> compatible = "qcom,sm8650-cnoc-main";
> reg = <0 0x01500000 0 0x14080>;
> @@ -3561,11 +3566,6 @@ mmss_noc: interconnect@1780000 {
> #interconnect-cells = <2>;
> };
>
> - rng: rng@10c3000 {
> - compatible = "qcom,sm8650-trng", "qcom,trng";
> - reg = <0 0x010c3000 0 0x1000>;
> - };
> -
> pcie0: pcie@1c00000 {
> device_type = "pci";
> compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
> @@ -3926,38 +3926,6 @@ pcie1_phy: phy@1c0e000 {
> status = "disabled";
> };
>
> - cryptobam: dma-controller@1dc4000 {
> - compatible = "qcom,bam-v1.7.0";
> - reg = <0 0x01dc4000 0 0x28000>;
> -
> - interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>;
> -
> - #dma-cells = <1>;
> -
> - iommus = <&apps_smmu 0x480 0>,
> - <&apps_smmu 0x481 0>;
> -
> - qcom,ee = <0>;
> - qcom,num-ees = <4>;
> - num-channels = <20>;
> - qcom,controlled-remotely;
> - };
> -
> - crypto: crypto@1dfa000 {
> - compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce";
> - reg = <0 0x01dfa000 0 0x6000>;
> -
> - interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
> - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> - interconnect-names = "memory";
> -
> - dmas = <&cryptobam 4>, <&cryptobam 5>;
> - dma-names = "rx", "tx";
> -
> - iommus = <&apps_smmu 0x480 0>,
> - <&apps_smmu 0x481 0>;
> - };
> -
> ufs_mem_phy: phy@1d80000 {
> compatible = "qcom,sm8650-qmp-ufs-phy";
> reg = <0 0x01d80000 0 0x2000>;
> @@ -4079,6 +4047,38 @@ ice: crypto@1d88000 {
> clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
> };
>
> + cryptobam: dma-controller@1dc4000 {
> + compatible = "qcom,bam-v1.7.0";
> + reg = <0 0x01dc4000 0 0x28000>;
> +
> + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>;
> +
> + #dma-cells = <1>;
> +
> + iommus = <&apps_smmu 0x480 0>,
> + <&apps_smmu 0x481 0>;
> +
> + qcom,ee = <0>;
> + qcom,num-ees = <4>;
> + num-channels = <20>;
> + qcom,controlled-remotely;
> + };
> +
> + crypto: crypto@1dfa000 {
> + compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce";
> + reg = <0 0x01dfa000 0 0x6000>;
> +
> + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "memory";
> +
> + dmas = <&cryptobam 4>, <&cryptobam 5>;
> + dma-names = "rx", "tx";
> +
> + iommus = <&apps_smmu 0x480 0>,
> + <&apps_smmu 0x481 0>;
> + };
> +
> tcsr_mutex: hwlock@1f40000 {
> compatible = "qcom,tcsr-mutex";
> reg = <0 0x01f40000 0 0x20000>;
> @@ -4962,6 +4962,176 @@ opp-202000000 {
> };
> };
>
> + usb_1_hsphy: phy@88e3000 {
> + compatible = "qcom,sm8650-snps-eusb2-phy",
> + "qcom,sm8550-snps-eusb2-phy";
> + reg = <0 0x088e3000 0 0x154>;
> +
> + clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
> + clock-names = "ref";
> +
> + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> +
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + usb_dp_qmpphy: phy@88e8000 {
> + compatible = "qcom,sm8650-qmp-usb3-dp-phy";
> + reg = <0 0x088e8000 0 0x3000>;
> +
> + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> + clock-names = "aux",
> + "ref",
> + "com_aux",
> + "usb3_pipe";
> +
> + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
> + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
> + reset-names = "phy",
> + "common";
> +
> + power-domains = <&gcc USB3_PHY_GDSC>;
> +
> + #clock-cells = <1>;
> + #phy-cells = <1>;
> +
> + orientation-switch;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + usb_dp_qmpphy_out: endpoint {
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + usb_dp_qmpphy_usb_ss_in: endpoint {
> + remote-endpoint = <&usb_1_dwc3_ss>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + usb_dp_qmpphy_dp_in: endpoint {
> + remote-endpoint = <&mdss_dp0_out>;
> + };
> + };
> + };
> + };
> +
> + usb_1: usb@a6f8800 {
> + compatible = "qcom,sm8650-dwc3", "qcom,dwc3";
> + reg = <0 0x0a6f8800 0 0x400>;
> +
> + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,
> + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
> + <&pdc 14 IRQ_TYPE_EDGE_RISING>,
> + <&pdc 15 IRQ_TYPE_EDGE_RISING>,
> + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "pwr_event",
> + "hs_phy_irq",
> + "dp_hs_phy_irq",
> + "dm_hs_phy_irq",
> + "ss_phy_irq";
> +
> + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>,
> + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
> + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> + <&tcsr TCSR_USB3_CLKREF_EN>;
> + clock-names = "cfg_noc",
> + "core",
> + "iface",
> + "sleep",
> + "mock_utmi",
> + "xo";
> +
> + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>;
> + assigned-clock-rates = <19200000>, <200000000>;
> +
> + resets = <&gcc GCC_USB30_PRIM_BCR>;
> +
> + interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
> + interconnect-names = "usb-ddr",
> + "apps-usb";
> +
> + power-domains = <&gcc USB30_PRIM_GDSC>;
> + required-opps = <&rpmhpd_opp_nom>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + status = "disabled";
> +
> + usb_1_dwc3: usb@a600000 {
> + compatible = "snps,dwc3";
> + reg = <0 0x0a600000 0 0xcd00>;
> +
> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>;
> +
> + iommus = <&apps_smmu 0x40 0>;
> +
> + phys = <&usb_1_hsphy>,
> + <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
> + phy-names = "usb2-phy",
> + "usb3-phy";
> +
> + snps,hird-threshold = /bits/ 8 <0x0>;
> + snps,usb2-gadget-lpm-disable;
> + snps,dis_u2_susphy_quirk;
> + snps,dis_enblslpm_quirk;
> + snps,dis-u1-entry-quirk;
> + snps,dis-u2-entry-quirk;
> + snps,is-utmi-l1-suspend;
> + snps,usb3_lpm_capable;
> + snps,usb2-lpm-disable;
> + snps,has-lpm-erratum;
> + tx-fifo-resize;
> +
> + dma-coherent;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + usb_1_dwc3_hs: endpoint {
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + usb_1_dwc3_ss: endpoint {
> + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
> + };
> + };
> + };
> + };
> + };
> +
> iris: video-codec@aa00000 {
> compatible = "qcom,sm8650-iris";
> reg = <0 0x0aa00000 0 0xf0000>;
> @@ -5580,176 +5750,6 @@ dispcc: clock-controller@af00000 {
> #power-domain-cells = <1>;
> };
>
> - usb_1_hsphy: phy@88e3000 {
> - compatible = "qcom,sm8650-snps-eusb2-phy",
> - "qcom,sm8550-snps-eusb2-phy";
> - reg = <0 0x088e3000 0 0x154>;
> -
> - clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
> - clock-names = "ref";
> -
> - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> -
> - #phy-cells = <0>;
> -
> - status = "disabled";
> - };
> -
> - usb_dp_qmpphy: phy@88e8000 {
> - compatible = "qcom,sm8650-qmp-usb3-dp-phy";
> - reg = <0 0x088e8000 0 0x3000>;
> -
> - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> - <&rpmhcc RPMH_CXO_CLK>,
> - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
> - <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> - clock-names = "aux",
> - "ref",
> - "com_aux",
> - "usb3_pipe";
> -
> - resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
> - <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
> - reset-names = "phy",
> - "common";
> -
> - power-domains = <&gcc USB3_PHY_GDSC>;
> -
> - #clock-cells = <1>;
> - #phy-cells = <1>;
> -
> - orientation-switch;
> -
> - status = "disabled";
> -
> - ports {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - port@0 {
> - reg = <0>;
> -
> - usb_dp_qmpphy_out: endpoint {
> - };
> - };
> -
> - port@1 {
> - reg = <1>;
> -
> - usb_dp_qmpphy_usb_ss_in: endpoint {
> - remote-endpoint = <&usb_1_dwc3_ss>;
> - };
> - };
> -
> - port@2 {
> - reg = <2>;
> -
> - usb_dp_qmpphy_dp_in: endpoint {
> - remote-endpoint = <&mdss_dp0_out>;
> - };
> - };
> - };
> - };
> -
> - usb_1: usb@a6f8800 {
> - compatible = "qcom,sm8650-dwc3", "qcom,dwc3";
> - reg = <0 0x0a6f8800 0 0x400>;
> -
> - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,
> - <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
> - <&pdc 14 IRQ_TYPE_EDGE_RISING>,
> - <&pdc 15 IRQ_TYPE_EDGE_RISING>,
> - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "pwr_event",
> - "hs_phy_irq",
> - "dp_hs_phy_irq",
> - "dm_hs_phy_irq",
> - "ss_phy_irq";
> -
> - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
> - <&gcc GCC_USB30_PRIM_MASTER_CLK>,
> - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
> - <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
> - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> - <&tcsr TCSR_USB3_CLKREF_EN>;
> - clock-names = "cfg_noc",
> - "core",
> - "iface",
> - "sleep",
> - "mock_utmi",
> - "xo";
> -
> - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> - <&gcc GCC_USB30_PRIM_MASTER_CLK>;
> - assigned-clock-rates = <19200000>, <200000000>;
> -
> - resets = <&gcc GCC_USB30_PRIM_BCR>;
> -
> - interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
> - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> - &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
> - interconnect-names = "usb-ddr",
> - "apps-usb";
> -
> - power-domains = <&gcc USB30_PRIM_GDSC>;
> - required-opps = <&rpmhpd_opp_nom>;
> -
> - #address-cells = <2>;
> - #size-cells = <2>;
> - ranges;
> -
> - status = "disabled";
> -
> - usb_1_dwc3: usb@a600000 {
> - compatible = "snps,dwc3";
> - reg = <0 0x0a600000 0 0xcd00>;
> -
> - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>;
> -
> - iommus = <&apps_smmu 0x40 0>;
> -
> - phys = <&usb_1_hsphy>,
> - <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
> - phy-names = "usb2-phy",
> - "usb3-phy";
> -
> - snps,hird-threshold = /bits/ 8 <0x0>;
> - snps,usb2-gadget-lpm-disable;
> - snps,dis_u2_susphy_quirk;
> - snps,dis_enblslpm_quirk;
> - snps,dis-u1-entry-quirk;
> - snps,dis-u2-entry-quirk;
> - snps,is-utmi-l1-suspend;
> - snps,usb3_lpm_capable;
> - snps,usb2-lpm-disable;
> - snps,has-lpm-erratum;
> - tx-fifo-resize;
> -
> - dma-coherent;
> -
> - ports {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - port@0 {
> - reg = <0>;
> -
> - usb_1_dwc3_hs: endpoint {
> - };
> - };
> -
> - port@1 {
> - reg = <1>;
> -
> - usb_1_dwc3_ss: endpoint {
> - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
> - };
> - };
> - };
> - };
> - };
> -
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,sm8650-pdc", "qcom,pdc";
> reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
On 7/27/25 9:36 PM, Krzysztof Kozlowski wrote: > Qualcomm DTS uses sorting of MMIO nodes by the unit address, so move > few nodes in SM8650 DTSI to fix that. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Konrad
© 2016 - 2025 Red Hat, Inc.