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([178.197.203.90]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af6358a1c23sm318267066b.51.2025.07.27.12.36.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Jul 2025 12:36:59 -0700 (PDT) From: Krzysztof Kozlowski To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH] arm64: dts: qcom: sm8650: Sort nodes by unit address Date: Sun, 27 Jul 2025 21:36:53 +0200 Message-ID: <20250727193652.4029-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.48.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=11920; i=krzysztof.kozlowski@linaro.org; h=from:subject; bh=pCQCdRmlqteGXO1dI3JhZJOwDdd/l/sBFMVSJ+tKS4c=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBohn/U3EEL9lsA4gGgyw4soEmQ+T9mPFjc51imq SGyybgk7lOJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaIZ/1AAKCRDBN2bmhouD 178DD/4lZF18/08Yzvzw4qiqtSF/pGbR/jJj2qVZaM/GpMpRi+GufSA4BeTgMrFK7oxYRr0pc0S 7TevAv373OoKlhYRsE8PNguNRvDwcfLrqPU5XbVcXS/nh0DLMpJMpMbrQRjl0OpcxBh+NpMXmsF csL2DC9rs3f30DTHY4/S2+z+khXMyapTVf9I8pum+3uB6JFg/pYnxsYjKwSYFw2IMQm8YtxQNWH vk7Bkq8q0PX9cpWz99MqNo2EL6jwa5DHh+W2rYcynAJVCEWunj3lKLzEi8x60DXykI6nXOZhCw3 kn4bv2LnE1LrNn29y6sTTAI9v+ZmcnhJuq+Rc3wl4DwkpoEIQsm6TNBk0DoWNU3AhShfA2QROHn y11Vtzcv5x60DQYmYVZfK7ZkPseCuMR6YJvRDLjFui4z3hGkiK+qJYnd2of43LehvtjA498J0Mn zO6K0ywoDSupG3yndZP5a0UasP11oeFm5XBoWVDFPi++ZDdXvQA8e0D+u0o1O9HwmhHXdMac29v 2O72/lzLDFnhum7PL7np7WG/ftYI+i5JCLSYuqSoI1pMN5AMfzuGBTk7veCm1CZrRlyrN5HZBZR 2MfSrK6AE1jY4NBgPtiOb3xkYHDaoLdM4TX9oDzSEwkQWHYrnicjEKeB87LNSzVJ7eeG71bg35F ZgD3tpNChMWjR4Q== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Qualcomm DTS uses sorting of MMIO nodes by the unit address, so move few nodes in SM8650 DTSI to fix that. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 414 +++++++++++++-------------- 1 file changed, 207 insertions(+), 207 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index e14d3d778b71..2360d560dc86 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3490,6 +3490,11 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, }; }; =20 + rng: rng@10c3000 { + compatible =3D "qcom,sm8650-trng", "qcom,trng"; + reg =3D <0 0x010c3000 0 0x1000>; + }; + cnoc_main: interconnect@1500000 { compatible =3D "qcom,sm8650-cnoc-main"; reg =3D <0 0x01500000 0 0x14080>; @@ -3561,11 +3566,6 @@ mmss_noc: interconnect@1780000 { #interconnect-cells =3D <2>; }; =20 - rng: rng@10c3000 { - compatible =3D "qcom,sm8650-trng", "qcom,trng"; - reg =3D <0 0x010c3000 0 0x1000>; - }; - pcie0: pcie@1c00000 { device_type =3D "pci"; compatible =3D "qcom,pcie-sm8650", "qcom,pcie-sm8550"; @@ -3926,38 +3926,6 @@ pcie1_phy: phy@1c0e000 { status =3D "disabled"; }; =20 - cryptobam: dma-controller@1dc4000 { - compatible =3D "qcom,bam-v1.7.0"; - reg =3D <0 0x01dc4000 0 0x28000>; - - interrupts =3D ; - - #dma-cells =3D <1>; - - iommus =3D <&apps_smmu 0x480 0>, - <&apps_smmu 0x481 0>; - - qcom,ee =3D <0>; - qcom,num-ees =3D <4>; - num-channels =3D <20>; - qcom,controlled-remotely; - }; - - crypto: crypto@1dfa000 { - compatible =3D "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce"; - reg =3D <0 0x01dfa000 0 0x6000>; - - interconnects =3D <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names =3D "memory"; - - dmas =3D <&cryptobam 4>, <&cryptobam 5>; - dma-names =3D "rx", "tx"; - - iommus =3D <&apps_smmu 0x480 0>, - <&apps_smmu 0x481 0>; - }; - ufs_mem_phy: phy@1d80000 { compatible =3D "qcom,sm8650-qmp-ufs-phy"; reg =3D <0 0x01d80000 0 0x2000>; @@ -4079,6 +4047,38 @@ ice: crypto@1d88000 { clocks =3D <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; =20 + cryptobam: dma-controller@1dc4000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0 0x01dc4000 0 0x28000>; + + interrupts =3D ; + + #dma-cells =3D <1>; + + iommus =3D <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + + qcom,ee =3D <0>; + qcom,num-ees =3D <4>; + num-channels =3D <20>; + qcom,controlled-remotely; + }; + + crypto: crypto@1dfa000 { + compatible =3D "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce"; + reg =3D <0 0x01dfa000 0 0x6000>; + + interconnects =3D <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "memory"; + + dmas =3D <&cryptobam 4>, <&cryptobam 5>; + dma-names =3D "rx", "tx"; + + iommus =3D <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + }; + tcsr_mutex: hwlock@1f40000 { compatible =3D "qcom,tcsr-mutex"; reg =3D <0 0x01f40000 0 0x20000>; @@ -4962,6 +4962,176 @@ opp-202000000 { }; }; =20 + usb_1_hsphy: phy@88e3000 { + compatible =3D "qcom,sm8650-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg =3D <0 0x088e3000 0 0x154>; + + clocks =3D <&tcsr TCSR_USB2_CLKREF_EN>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_dp_qmpphy: phy@88e8000 { + compatible =3D "qcom,sm8650-qmp-usb3-dp-phy"; + reg =3D <0 0x088e8000 0 0x3000>; + + clocks =3D <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names =3D "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets =3D <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names =3D "phy", + "common"; + + power-domains =3D <&gcc USB3_PHY_GDSC>; + + #clock-cells =3D <1>; + #phy-cells =3D <1>; + + orientation-switch; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_dp_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb_dp_qmpphy_usb_ss_in: endpoint { + remote-endpoint =3D <&usb_1_dwc3_ss>; + }; + }; + + port@2 { + reg =3D <2>; + + usb_dp_qmpphy_dp_in: endpoint { + remote-endpoint =3D <&mdss_dp0_out>; + }; + }; + }; + }; + + usb_1: usb@a6f8800 { + compatible =3D "qcom,sm8650-dwc3", "qcom,dwc3"; + reg =3D <0 0x0a6f8800 0 0x400>; + + interrupts-extended =3D <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, + <&pdc 14 IRQ_TYPE_EDGE_RISING>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&tcsr TCSR_USB3_CLKREF_EN>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks =3D <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <200000000>; + + resets =3D <&gcc GCC_USB30_PRIM_BCR>; + + interconnects =3D <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "usb-ddr", + "apps-usb"; + + power-domains =3D <&gcc USB30_PRIM_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + usb_1_dwc3: usb@a600000 { + compatible =3D "snps,dwc3"; + reg =3D <0 0x0a600000 0 0xcd00>; + + interrupts =3D ; + + iommus =3D <&apps_smmu 0x40 0>; + + phys =3D <&usb_1_hsphy>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names =3D "usb2-phy", + "usb3-phy"; + + snps,hird-threshold =3D /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; + + dma-coherent; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb_1_dwc3_ss: endpoint { + remote-endpoint =3D <&usb_dp_qmpphy_usb_ss_in>; + }; + }; + }; + }; + }; + iris: video-codec@aa00000 { compatible =3D "qcom,sm8650-iris"; reg =3D <0 0x0aa00000 0 0xf0000>; @@ -5580,176 +5750,6 @@ dispcc: clock-controller@af00000 { #power-domain-cells =3D <1>; }; =20 - usb_1_hsphy: phy@88e3000 { - compatible =3D "qcom,sm8650-snps-eusb2-phy", - "qcom,sm8550-snps-eusb2-phy"; - reg =3D <0 0x088e3000 0 0x154>; - - clocks =3D <&tcsr TCSR_USB2_CLKREF_EN>; - clock-names =3D "ref"; - - resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - - usb_dp_qmpphy: phy@88e8000 { - compatible =3D "qcom,sm8650-qmp-usb3-dp-phy"; - reg =3D <0 0x088e8000 0 0x3000>; - - clocks =3D <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names =3D "aux", - "ref", - "com_aux", - "usb3_pipe"; - - resets =3D <&gcc GCC_USB3_PHY_PRIM_BCR>, - <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; - reset-names =3D "phy", - "common"; - - power-domains =3D <&gcc USB3_PHY_GDSC>; - - #clock-cells =3D <1>; - #phy-cells =3D <1>; - - orientation-switch; - - status =3D "disabled"; - - ports { - #address-cells =3D <1>; - #size-cells =3D <0>; - - port@0 { - reg =3D <0>; - - usb_dp_qmpphy_out: endpoint { - }; - }; - - port@1 { - reg =3D <1>; - - usb_dp_qmpphy_usb_ss_in: endpoint { - remote-endpoint =3D <&usb_1_dwc3_ss>; - }; - }; - - port@2 { - reg =3D <2>; - - usb_dp_qmpphy_dp_in: endpoint { - remote-endpoint =3D <&mdss_dp0_out>; - }; - }; - }; - }; - - usb_1: usb@a6f8800 { - compatible =3D "qcom,sm8650-dwc3", "qcom,dwc3"; - reg =3D <0 0x0a6f8800 0 0x400>; - - interrupts-extended =3D <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, - <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, - <&pdc 14 IRQ_TYPE_EDGE_RISING>, - <&pdc 15 IRQ_TYPE_EDGE_RISING>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names =3D "pwr_event", - "hs_phy_irq", - "dp_hs_phy_irq", - "dm_hs_phy_irq", - "ss_phy_irq"; - - clocks =3D <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&tcsr TCSR_USB3_CLKREF_EN>; - clock-names =3D "cfg_noc", - "core", - "iface", - "sleep", - "mock_utmi", - "xo"; - - assigned-clocks =3D <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates =3D <19200000>, <200000000>; - - resets =3D <&gcc GCC_USB30_PRIM_BCR>; - - interconnects =3D <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names =3D "usb-ddr", - "apps-usb"; - - power-domains =3D <&gcc USB30_PRIM_GDSC>; - required-opps =3D <&rpmhpd_opp_nom>; - - #address-cells =3D <2>; - #size-cells =3D <2>; - ranges; - - status =3D "disabled"; - - usb_1_dwc3: usb@a600000 { - compatible =3D "snps,dwc3"; - reg =3D <0 0x0a600000 0 0xcd00>; - - interrupts =3D ; - - iommus =3D <&apps_smmu 0x40 0>; - - phys =3D <&usb_1_hsphy>, - <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; - phy-names =3D "usb2-phy", - "usb3-phy"; - - snps,hird-threshold =3D /bits/ 8 <0x0>; - snps,usb2-gadget-lpm-disable; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,is-utmi-l1-suspend; - snps,usb3_lpm_capable; - snps,usb2-lpm-disable; - snps,has-lpm-erratum; - tx-fifo-resize; - - dma-coherent; - - ports { - #address-cells =3D <1>; - #size-cells =3D <0>; - - port@0 { - reg =3D <0>; - - usb_1_dwc3_hs: endpoint { - }; - }; - - port@1 { - reg =3D <1>; - - usb_1_dwc3_ss: endpoint { - remote-endpoint =3D <&usb_dp_qmpphy_usb_ss_in>; - }; - }; - }; - }; - }; - pdc: interrupt-controller@b220000 { compatible =3D "qcom,sm8650-pdc", "qcom,pdc"; reg =3D <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; --=20 2.48.1